2004
DOI: 10.1021/nl0481573
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Controlled Fabrication of Silicon Nanowires by Electron Beam Lithography and Electrochemical Size Reduction

Abstract: We demonstrate that electrochemical size reduction can be used for precisely controlled fabrication of silicon nanowires of widths approaching the 10 nm regime. The scheme can, in principle, be applied to wires defined by optical lithography but is here demonstrated for wires of approximately 100-200 nm width, defined by electron beam lithography. As for electrochemical etching of bulk silicon, the etching can be tuned both to the pore formation regime as well as to electropolishing. By in-situ optical and ele… Show more

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Cited by 122 publications
(73 citation statements)
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“…Sub-ten-nanometer pattern generation commonly utilizes electron beam lithography, which is time-consuming and expensive [14,15]. Another popular Si nanofabrication technology is standard RIE, which is aided by advanced lithography techniques, [16,17] such as photolithography, nanosphere lithography, and nanoimprint lithography.…”
Section: Resultsmentioning
confidence: 99%
“…Sub-ten-nanometer pattern generation commonly utilizes electron beam lithography, which is time-consuming and expensive [14,15]. Another popular Si nanofabrication technology is standard RIE, which is aided by advanced lithography techniques, [16,17] such as photolithography, nanosphere lithography, and nanoimprint lithography.…”
Section: Resultsmentioning
confidence: 99%
“…Non-radiative recombination through surface defect states can degrade light emission properties, while an undesired charge trapping can be detrimental to the conductivity performance. We note that, although thermal oxidation is a well-known method for size reduction of silicon nanostructures [13], here it is only used for surface passivation since the initial nanostructure size is already below 10 nm.…”
Section: Resultsmentioning
confidence: 99%
“…A conventional electron beam (e-beam) lithography patterning with a polymer resist, on the other hand, is typically reproducible in the range abovẽ 15-20 nm [12]. Hence, nanostructures fabricated by these methods require additional size-reduction steps to reach a sub-10 nm range [13]. A scanning probe lithography for local oxidation of silicon has similar limitations [14].…”
Section: Introductionmentioning
confidence: 99%
“…Silicon nanowires are one of the most important 1D nanomaterials under development, and have recently attracted further attention because of their high compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology, leading to possible integration with electronic devices [5][6][7]. Several methods have been used to prepare Si nanowires, including chemical vapor deposition [8][9], solution phase synthesis [10], lithography related etching methods [11], photolithography techniques [12][13][14], and scanning tunneling microscopy [15][16]. The vapor-liquid-solid (VLS) method that uses gold (Au) as a catalyst is one of the most prevalent approaches to Si nanowire synthesis [17][18][19][20].…”
Section: Intoroductionmentioning
confidence: 99%