Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Kumar, M. Jagadesh; Sahay, Shubham

doi:10.1109/ted.2016.2577050

Cited by 69 publications

(6 citation statements)

References 27 publications

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“…Consequently, the embedded layer operates as the base side of the intrinsic BJT, with the high density of source as the emitter and high density of drain as the collector. [ 40 ] This phenomenon dramatically decreases the intrinsic BJT value, causing to reducing parasitic BJT.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Madadi

Orouji

2022

Physica Status Solidi (a)

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This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Madadi

Orouji

2022

Physica Status Solidi (a)

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“…Because of the enhanced vertical field, an additional layer is formed on the existing drain side depletion layer, which causes a portion of the overall potential between the source and drain to drop across the additional depletion layer. Because of the modulation in the vertical electric field inside the overlapped drain side of DEBG-NC-TFET, recombination, and excitation of various mobile charge carriers are carried out [32]. The vertical field dominates in the formation of additional depletion width within the overlapping drain region, which further results in an increment of the barrier region at the D/C tunneling interface.…”

Section: Characteristicsmentioning

confidence: 99%

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

Pathakamuri,

Pandey

2023

Phys. Scr.

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In this paper, we present an extended back gate-on-drain negative capacitance TFET (DEBG-NC-TFET) for enhanced DC and analog/HF performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of the Ferroelectric layer (FEL) introduced into the gate-oxide layer of the device, without deteriorating other parameters of the device. This work examines the effects of various factors of NC, such as remnant polarization (Pr) and coercive electric field (Ec) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FEL, DEBG-NC-TFET is found to offer a huge reduction in IAMB with unchanged IOFF and ION as compared with those of the symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical electrical field induced in drain increases the depletion layer at channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only back gate overlaps the drain region of DG-NC-TFET.

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“…Since the channel carrier concentration is controlled by gate, the valence band and the conduction band are overlapped at the channel/drain interface and a lateral band‐to‐band tunneling (BTBT) of electrons occurs 18 that leads to gate induced drain leakage (GIDL) 20 and hence OFF‐state current increases. To decrease the OFF‐state leakage current caused by GIDL effect, many structures have been proposed such as a saddle JLFET with assisted gate, 24 dual‐material dual gate JL MOSFET embedded with low doped buried layer, 25 charge plasma JLFET with contact engineering, 26 JLFET with hybrid channel, 27 JLFET with high‐k BOX, 28 JLFET with dual material gate, 29 JLFET with core‐shell architecture 30 and so on.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of short channel effects immune JLFET with enhanced drive current

Raj¹,

Singh

Sharma³

2023

Int J Numerical Modelling

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This manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).

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Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Cited by 69 publications

References 27 publications

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

Performance analysis of short channel effects immune JLFET with enhanced drive current

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