Controlling the threshold voltage of a semiconductor field-effect transistor by gating its graphene gate

Anzi, Luca; Tuktamyshev, Artur; Fedorov, Alexey; Zurutuza, Amaia; Sanguinetti, S.; Sordan, Roman

doi:10.1038/s41699-022-00302-y

Cited by 8 publications

(6 citation statements)

References 36 publications

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“…It is noteworthy that the off-state current (I OFF ) is maintained in the range of 0.22 to 0.44 pA, much smaller than that in planar 2D-FETs. [53,54] This is because of the large conduction band offset and barrier height at MoS 2 /WSe 2 junction, giving rise to the complete off-state of device, [55] as discussed in detail later. Figure 2c shows the transfer curves by sweeping V TG forward and backward, revealing negligible hysteresis with memory window of only 30 mV in the subthreshold region, which is comparable with the presently advanced GaN-high electron mobility transistor (HEMT) and MoS 2 -multi bridge channel FET(MBCFET).…”

Section: Device Scheme and Characterizationmentioning

confidence: 99%

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Deng

Sun

et al. 2023

Adv Funct Materials

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With continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

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Section: Device Scheme and Characterizationmentioning

confidence: 99%

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Deng

Sun

et al. 2023

Adv Funct Materials

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“…This also determines the tolerance of logic states to electrical noise. Various solutions have been tested previously such as the dielectric constant of the gate insulator, surface functionalization of the gate insulator, local doping of semiconductor, multiple-layer gate electrode, etc. Most of these face challenges while scaling devices .…”

Section: Introductionmentioning

confidence: 99%

Selective Operation of Enhancement and Depletion Modes of Nanoscale Field-Effect Transistors

Sagade

2024

ACS Appl. Electron. Mater.

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Most of the CMOS field-effect transistors (FETs) are in enhancement mode, absence of charge carriers in the channel at zero gate voltage, to reduce power consumption. In principle, depletion mode transistors have higher currents than the enhancement mode due to ample charge carrier density. For high-frequency applications, the off-state of FET is not a mandatory requirement. Rather the presence of a channel at zero gate bias and sufficiently large saturation mobility is advantageous. Here, we demonstrate that by selecting a particular work function for a gate metal, threshold voltages of the FETs can be changed from negative to positive values that is selective switching between enhancement mode and depletion mode of the operation. The devices are fabricated with Al, Si, and Au gate metals with Au source–drain metal. Well-known p-type molecular semiconductor dinaphthothienothiophene (DNTT) is deposited by evaporation under high vacuum. It is observed that depending on the low- or high-work functions of the gate metal, the channel is absent or present at zero gate voltage. For work functions below and above 4.8 eV, the FET is in enhancement and depletion modes, respectively. We also show that this effect can be strongly observed for thin dielectrics. The experimental results are complemented by TCAD device simulations. This work will be crucial for high-frequency and precision logic-gate applications of organic as well as 2D materials devices.

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“…However, oxide-semiconductor-based thin-film transistors (TFTs) suffer from severe threshold shifts during operation; therefore, compensation circuits are generally incorporated in their applications [5,6]. The threshold voltage (V th ) of TFTs is a gate voltage required to turn the devices on and is estimated using several methods, including a commonly used linear fitting method [7,8], a field-effect mobility derivation method [9], and a constant-current method [10]. However, the definition of the threshold voltage of TFTs is ambiguous.…”

Section: Introductionmentioning

confidence: 99%

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

Yoon

2023

Materials

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In this paper, we present a threshold-voltage extraction method for zinc oxide (ZnO) thin-film transistors (TFTs). Bottom-gate atomic-layer-deposited ZnO TFTs exhibit typical n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, unreliable threshold voltage. We posit that this obscure threshold voltage is attributed to the localized trap states of ZnO TFTs, of which the field-effect mobility can be expressed as a gate-bias-dependent power law. Hence, we derived the current–voltage relationship by dividing the drain current with the transconductance to rule out the gate-bias-dependent factors and successfully extract the reliable threshold voltage. Furthermore, we investigated the temperature-dependent characteristics of the ZnO TFTs to validate that the observed threshold voltage was genuine. Notably, the required activation energies from the low-temperature measurements displayed an abrupt decrease at the threshold voltage, which was attributed to the conduction route change from diffusion to drift. Thus, we conclude that the reliable threshold voltage of accumulation-mode ZnO TFTs can be determined using a gate-bias-dependent factor-removed current–voltage relationship with a low-temperature analysis.

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Controlling the threshold voltage of a semiconductor field-effect transistor by gating its graphene gate

Cited by 8 publications

References 36 publications

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Selective Operation of Enhancement and Depletion Modes of Nanoscale Field-Effect Transistors

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

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