Cooling three-dimensional integrated circuits using power delivery networks

Wei, Hai; Wu, Tung-Yu; Sekar, Deepak; Cronquist, B.; Pease, R. F. W.; Mitra, Subhasish

doi:10.1109/iedm.2012.6479040

Cited by 36 publications

(12 citation statements)

References 8 publications

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“…Yet, in a modern microprocessor, the actual generated heat is at the active area of the devices and is caused by the flow of current in these areas leading to the highest temperature in an electronic package (the chip junction temperature). Nonetheless, these results can be very useful for further explorations aimed at implementing these new ultra-thin silicon (substrate) with micro-air channel network in a 3D IC structure 55,56 where another substrate beneath heating-up is analogous to the thermal stage used in this experiment.…”

Section: Aip Advances 5 127115 (2015)mentioning

confidence: 99%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

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Section: Aip Advances 5 127115 (2015)mentioning

confidence: 99%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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“…Tier0 in monolithic 3D is much cooler than Tier0 in TSV-based 3D as there is no bonding layer obstruction while Tier1 of monolithic 3D IC is hotter than Tier1 of TSV-based 3D IC because of the oxide. Wei et al also compared TSV based 3D IC with monolithic 3D ICs but did not consider the underfill layer [5]. The mass production of TSV-based 3D ICs without any underfill is highly unlikely due to stress related issues.…”

Section: Temperature Map Comparisonsmentioning

confidence: 96%

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

Samal

Panth

Samadi

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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In this paper, we present a comprehensive study of the unique thermal behavior in monolithic 3D ICs. In particular, we study the impact of the thin inter-layer dielectric (ILD) between the device tiers on vertical thermal coupling. In addition, we develop a fast and accurate compact full-chip thermal analysis model based on non-linear regression technique. Our model is extremely fast and highly accurate with an error of less than 5%. This model is incorporated into a thermal-aware 3D-floorplanner that runs without significant runtime overhead. We observe up to 22% reduction in the maximum temperature with insignificant area and performance overhead.

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“…Thus, pairs of metal 7/8 width and metal 1/2 width that satisfy a specific target resistance can be identified. To determine target resistance, a power density of 50 W/cm 2 (corresponds to OpenSPARC T2 processor [29]) is considered. Scaling this power density for the physical area and assuming that the power supply voltage is 1 V, the power supply current is approximated as 31.25 mA.…”

Section: Design Space Exploration In the Presence Of Local Power Netwmentioning

confidence: 99%

Quantifying the effect of local interconnects on on-chip power distribution

Salman

2015

Microelectronics Journal

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Cooling three-dimensional integrated circuits using power delivery networks

Cited by 36 publications

References 8 publications

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

Quantifying the effect of local interconnects on on-chip power distribution

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