Coordinate rotation based low complexity architecture for 3D Single Channel Independent Component Analysis

Yerrapragada, Jayesh B.; Olemann, Aditi; Acharyya, Amit; Ahamed, Shaik Rafi

doi:10.1109/embc.2013.6611249

Cited by 2 publications

(1 citation statement)

References 17 publications

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“…With the advent of mobile and communication technologies, advancement in the VLSI industries leading to the emerging field of Cyber physical systems and Internet of things are gradually making the remote personalized CVD monitoring systems a reality. In such remote health monitoring scenario the underlying principle is to capture the vital signs from the body, processing it onchip and transmit it when necessary [2]. However, the vital signs are mixed with noise and other physiological artifacts, which therefore need computationally intensive signal processing to retrieve the physiological information back from the composite.…”

Section: Introductionmentioning

confidence: 99%

Low complexity underdetermined blind source separation system architecture for emerging remote healthcare applications

Mopuri

Reddy

et al. 2014

2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society

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In this paper, we have proposed a low complexity architecture for the Under-determined Blind Source Separation (UBSS) algorithm targeting remote healthcare applications. UBSS algorithm, departing from the typical BSS convention-equal number of the sources and sensors present, which is of tremendous interest in the field of Biomedical signal processing especially for remote health care applications. Since such applications are constrained by the on-chip area and power consumption limitation due to the battery backup, a low complexity architecture needs to be formulated. In this paper, firstly we have introduced UBSS architecture, followed by the identification of the most computationally intensive module N-point Discrete Hilbert Transform (DHT) and finally proposed a low complexity DHT architecture design to make the entire UBSS architecture suitable for such resource constrained applications. The proposed DHT architecture implementation and experimental comparison results show that the proposed design saves 50.28%, 48.40% and 46.27% on-chip area and 53.25%, 48.01% and 45.95% power consumption when compared to the state of the art method for N = 32, 64 and 128 respectively. Furthermore the proposed DHT architecture works for N = 2m point, but the state of art architecture works for N = 4m point, where m is an integer.

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Section: Introductionmentioning

confidence: 99%