Coordinated energy management in heterogeneous processors

Paul, Indrani; Ravi, Vignesh T.; Manne, Srilatha; Arora, Manish; Yalamanchili, Sudhakar

doi:10.1145/2503210.2503227

Cited by 23 publications

(15 citation statements)

References 32 publications

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“…For desktop platforms, there has also been e orts to exploit CPU and GPU cores present within a single chip [28,35,36]. In these platforms, coordination of CPU and GPU cores needs more consideration.…”

Section: Related Workmentioning

confidence: 99%

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs

Singh

Prakash

Basireddy

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) containing CPU and GPU cores are typically required to execute applications concurrently. However, as will be shown in this paper, existing approaches are not well suited for concurrent applications as they are developed either by considering only a single application or they do not exploit both CPU and GPU cores at the same time. In this paper, we propose an energy-e cient run-time mapping and thread partitioning approach for executing concurrent OpenCL applications on both GPU and GPU cores while satisfying performance requirements. Depending upon the performance requirements, for each concurrently executing application, the mapping process nds the appropriate number of CPU cores and operating frequencies of CPU and GPU cores, and the partitioning process identi es an e cient partitioning of the applications' threads between CPU and GPU cores. We validate the proposed approach experimentally on the Odroid-XU3 hardware platform with various mixes of applications from the Polybench benchmark suite. Additionally, a case-study is performed with a real-world application SLAMBench. Results show an average energy saving of 32% compared to existing approaches while still satisfying the performance requirements.

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Section: Related Workmentioning

confidence: 99%

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs

Singh

Prakash

Basireddy

et al. 2017

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…For desktop platforms, there has also been efforts to exploit CPU and GPU cores present within a single chip [19,27,28]. In these platforms, coordination of CPU and GPU cores needs more consideration.…”

Section: State-of-the-artmentioning

confidence: 99%

“…In [28], similar AMD platform is used to perform coordinated CPU-GPU executions, but memory contention occurs due to access of the same bank in different patterns by the CPU and GPU. In [19], the problem of shared resources in AMD platforms is addressed. However, these efforts do not consider limited power budget that is available for embedded systems operating from batteries.…”

Section: State-of-the-artmentioning

confidence: 99%

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs

Wächter

Merrett

Al-Hashimi

et al. 2017

Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia

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Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) containing CPU and GPU cores are typically required to execute applications concurrently. Existing approaches exploit applications executing in CPU and GPU cores at the same time taking into account performance and energy consumption for mapping and partitioning. This paper presents a proposal for mapping and partitioning of applications in CPU-GPU MPSoCs taking into account the temperature behavior of the system. We evaluate the temperature profiling to partition the applications between CPU and GPU. The profiling is done by measuring the temperature of the CPU and GPU cores while executing different applications at different partitions. Results shown up to 13% savings of average temperature of the chip while maintaining performance requirements. A lower thermal behavior represents a better long-term reliability (lifetime) of the SoC.

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“…Pao et al [14] studied the opportunities for energy optimization via DVFS in integrated CPU-GPU architectures. Bailey et al [15] designed models for power and execution time, and applied them to optimize performance in power-capped execution scenarios by selecting the appropriate CPU or GPU and the optimal hardware-configuration for execution.…”

Section: Power and Energy Minimization Techniquesmentioning

confidence: 99%

Evaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics

Chalios

Nikolopoulos

Catalán³

et al. 2016

IET Computers & Digital Techniques

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The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.

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Coordinated energy management in heterogeneous processors

Cited by 23 publications

References 32 publications

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs

Evaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics

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