Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit

Abstract

This paper proposes a multi-core architecture for implementation of a unified chassis control (UCC) algorithm on a field programmable gate array (FPGA) which operates as a multi-core process. The proposed multi-core architecture aims to reduce the operating load and maximize the reliability for improving the performance of the UCC system. The proposed multi-core architecture supports distributed control with analytical and physical redundancy capabilities. The UCC algorithm used in this research consists of three parts: a supervisor, a main controller, and fault detection/isolation/tolerance control (FDI/FTC). These three components are implemented and evaluated with the multi-core process environment with the FPGA. An electronic control unit is configured by three MicroBlaze processors with FPGA, and a control area network (CAN) is also implemented for hardware-in-the-loop (HILS) evaluation. Three types of multi-core architectures, i.e. distributed processing, triple voting, and hybrid operation, are implemented to investigate the performance and reliability. A vehicle simulator and brake HILS are used to evaluate the proposed multi-core architectures. From the test results, it is shown that all of the proposed multi-core systems have better performance and improved reliability compared with the single core system. In particular, the hybrid operation architecture shows better reliability and performance compared with the other two multi-core architectures, distributed processing and triple voting.

FPGA Based Powertrain Control for Electric Vehicles

“…The first feature, high processing speed, enables a reduction in execution times of the motor control algorithm, which can been explored to increase the bandwidth of torque control (Takahashi & Goetz, 2004) and decrease the discretization effects of some control and estimation techniques (Delli Colli et al, 2010;Naouar et al, 2007). Similarly, the FPGA parallelism and modularity features open up new possibilities to incorporate multi-motor control in a single chip, a useful property in multi-axis robotic manipulator arm (Jung Uk et al, 2009) and in process control applications (Tazi et al, 1999), and develop fault tolerant control systems with physical redundancy (Seo et al, 2010). Furthermore, even software based solution implemented in DSPs relies on some special hardware peripherals to boost time critical tasks, e.g.…”