Coping with Variations through System-Level Design

Abstract

Manufacturing and operation-induced variations have emerged as a critical challenge in designing integrated circuits (ICs) under the nanometer technology regime. Most work on addressing variations has focused on device, circuit, and logic-level solutions. As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that variations have on IC performance, power, yield, and design time. Therefore, in recent years, the research community has shown great interest in techniques to address variations starting from the other end of the design process, i.e., at the system level. In this paper, we provide an overview of various techniques that we have developed for coping with variations through system-level design. The presented techniques include a paradigm for designing variationtolerant systems through critical path isolation for timing adaptiveness, application-specific techniques to achieve variation-tolerance by trading off quality of the result, variation-aware system-level power analysis, and system-level power management under variations. These techniques demonstrate that addressing variations during system-level design can greatly mitigate the effects of variations, enabling the design of integrated circuits in scaled technologies.

Power Yield Analysis Under Process and Temperature Variations

“…Also, denotes the nominal total leakage power in thermal grid at the reference temperature, and . The statistical behavior of the power consumption leads to variations in the operating temperature of each thermal grid which is modeled by the following random variable: (5) where is the total power in thermal grid , and is an element in the inverse of thermal admittance matrix ( ).…”

“…Some variation reduction techniques such as adaptive body bias and variation-tolerant microarchitecture mechanisms and their impact on power are considered in [5]. A fullchip leakage estimation is reported in [6], where some information such as the cell library, cell usage, and dimensions of the layout are applied to find the statistics of the leakage power.…”