Coplanar transmission lines on silicon substrates for the mm-wave applications

2014 9th European Microwave Integrated Circuit Conference

2014

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This paper presents optimization process, simulations and measurement results of a fully differential 60 GHz active down converter with resonating current bleeding in a 90 nm CMOS process. The circuit is thought to be used within a superheterodyne receiver with intermediate frequency at around 20 GHz, covering the four channels of the IEEE802.15.3c standard. Thanks to the careful optimization of the resonating current bleeding network, the quad introduced noise is minimized keeping the conversion gain and the required local oscillator power at reasonable values.

Section: Resonating Current Bleeding Network and Matching Networkmentioning

confidence: 99%

“…4. The whole design procedure has been performed by careful modeling of all the passive structures [2,3] assisted by electromagnetic (EM) simulations. The optimization of all the down converter parts is addressed within the following subsections.…”

Section: Introductionmentioning

confidence: 99%

A low noise fully differential 60 GHz CMOS active down converter with resonating current bleeding

Malignaggi

2014 9th European Microwave Integrated Circuit Conference

2014

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“…In this design, all the inductive elements are realized using shielded coplanar transmission lines (SCTL) [6]. A visual example of SCTL is given in Fig.…”

Section: I P a S S I V E S T R U C T U R E Smentioning

confidence: 99%

“…Beyond the requests of low-power consumption, a must for circuits thought to be used in portable devices, and wide bandwidth, essential in high-speed designs, a very low-noise figure together with very high-gain is requested to LNAs in order to improve the cleanliness of the received signal. The fulfillment of all the previous requirements can be satisfied only by a careful optimization of the transistor sizes and a precise modeling of the passive structures [4][5][6]. This paper presents the design of a 60 GHz four-stage fully differential LNA based on the common-source topology, using a commercial bulk 90 nm TSMC LP technology with f t and f max about 120 GHz.…”

Section: Introductionmentioning

confidence: 99%

A 60 GHz fully differential LNA in 90 nm CMOS technology

Malignaggi

Int. j. microw. wirel. technol.

2013

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The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm 2 pads included. The detailed design procedure and the achieved measurement results are presented in this work.

“…But the chip size and integration requirements of the new devices and the many limitations of the mm-wave region in the faces of off-chip matching network and combiner design, has pushed the circuit designers toward novel passive structure design techniques [1]- [2].…”

Section: Introductionmentioning

confidence: 99%

Integrated left- and right-handed passive structures for millimeter wave applications

Barbin

2015 17th International Conference on Transparent Optical Networks (ICTON)

2015

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This paper presents the design of different on-chip left-and right-handed transmission lines for millimeter application and based on lumped components, such as inductors and capacitors. Further, the utilization of the developed models in a Wilkinson combiner structures is investigated. An easy and straightforward procedure has also been presented to ease the inductor and capacitor value selection. All the structures are designed and realized on IHP 0.25 μm SiGe BiCMOS process. The results, extracted from the measurements, show a good agreement with the simulation. Moreover it verifies the utilization feasibility of this design technique in realization of the on-chip passive structures, such as combiners and matching networks, with minimum size and low loss. The achieved results show good matching and less than 1 dB insertion loss with more than 10 times active chip size reduction, for λ/4 line and Wilkinson combiner, by using this technique.