Wire bonding is key to high-quality IC assembly in semiconductor packaging. An electrical test was conducted before wire bonding. During the electrical test, the needle probes touched the surface of each bond pad resulting in a probe trace left, called probe marks. The probe mark on the bond pad affects the adhesion between the bond pad and copper ball. Generally, the bond ball can be removed easily under shear testing if the ratio of probe mark area to pad area is greater than 20%. A large probe mark causes a defect in the yield. However, rejecting the orders of wafer batches with large probe marks will result in a loss of market share and good relationships with clients. In order to find the optimal parameter settings for the batches of chips with probe mark areas larger than 20% and deal with multiple response problems, this study aims to optimize the parameters of operation for the IC with large probe marks in the wire bonding process to improve process capability and production yield. Response surface methodology (RSM) optimization with the desirability function approach was introduced into the central composite design to obtain the optimal process parameters efficiently and eliminate defects. The optimal parameter settings for the four factors were determined as follows: 90 mA bond power, 12 ms bond time, 10 g bond force, and 180 °C bond temperature. The validation testing confirms that optimal parameter settings increase yield from 98.84% to 99.94% with good process capability, helping companies improve quality, reduce defect costs, and improve customer relationships.