Copper Metallization for High Performance Silicon Technology

Abstract

▪ Abstract The increasingly rapid transition of the electronics industry to high-density, high-performance multifunctional microprocessor Si technology has precipitated migration to new materials alternatives that can satisfy stringent requirements. One of the recent innovations has been the substitution of copper for the standard aluminum-copper metal wiring in order to decrease resistance and tailor RC delay losses in the various hierarchies of the wiring network. This has been accomplished and the product shipped only since the fall of 1998, after more than a decade of intensive development. Critical fabrication innovations include the development of an electroplating process for the copper network, dual-damascence chem-mech polishing (CMP), and effective liner material for copper diffusion barrier and adhesion promotion. The present copper technology provides improved current-carrying capability by higher resistance to electromigration, no device contamination by copper migration, and the performance enhancement analytically predicted. This success of the shift to copper will accelerate the industry movement to finer features and more complex interconnect structures with sufficient device density and connectivity to integrate full systems on chips. The next innovation will be the introduction of low-dielectric constant material that, in combination with copper, will create added excitement as the industry learns how to utilize this new capability.

In situ investigation of the microstructure evolution in nanocrystalline copper electrodeposits at room temperature

“…A similar thickness dependence of the selfannealing kinetics has been observed previously. 6,7,[24][25][26][27] Supported by the observation of even slower kinetics observed for Cu deposited in damascene trenches, 8,28,29 the thickness dependence has been attributed to geometrical constraints due to trench and via structures and/or the interface and surface of the film. 8 This, however, does not explain the complete absence of self-annealing in the thinnest Cu layer, as observed in the present study, since the as-deposited crystallite sizes are considerably smaller than the layer thickness.…”

Reduction mechanisms of the CuO(111) surface through surface oxygen vacancy formation and hydrogen adsorption

“…1 A process to deposit a uniform and continuous thin film ( < 2 nm) of copper in high aspect ratio structures is desirable in order to meet the demands of current trends in integrated circuit technology. Deposition techniques including physical vapour deposition (PVD), 2 electrodeposition, 3 chemical vapour deposition (CVD), 4 and atomic layer 1-17 | 1 deposition (ALD) 5 have been applied with the aim of obtaining such a thin film. However, it is extremely difficult to deposit thin films of Cu at this thickness and instead islands of Cu tend to be more favourable.…”

“…5,7 Unfortunately, the typical temperature requirement for these reactions (200-400°C) causes dewetting which leads to discontinuous copper films. Recently, Sung et al reported thermal ALD of copper metal using the reaction of copper dimethylamino-2-propoxide [Cu(dmap) 2 ] and diethylzinc [ZnEt 2 ] at 100-120°C. 5 However, subsequent work reported that the parasitic chemical vapour deposition reaction of ZnEt 2 may lead to Zn incorporation into the copper thin film.…”

Rapid trench initiated recrystallization and stagnation in narrow Cu interconnect lines

“…After plating, the overburden above the trenches is also 111-textured, despite the random orientations found on the sidewall seed. 24 These differences have important implications for transformation kinetics, according to the recent work on electroplated films. Several such studies using high resolution x-ray diffraction found that films deposited on untextured seed layers recrystallized faster than their textured counterparts, but resulted in smaller final grain size and lower final 111 texture.…”