CORDIC-based VLSI architecture for real time implementation of flat top window

Kumar, Vikas; Ray, Kailash Chandra; Kumar, Preetam

doi:10.1016/j.micpro.2014.07.004

Cited by 12 publications

(18 citation statements)

References 24 publications

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“…For the large number of computations in Fourier coefficient V l and filter coefficient W l k , we use the well-known CORDIC algorithm [19], [20] that requires only shift and add operations during the iterative vector rotation algorithm implementation. The CORDIC algorithm is carried out by an iterative microrotation (called as prefixed angle α i ) stages and evaluated by only add and shift operation.…”

Section: Cordic Algorithmmentioning

confidence: 99%

Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

Kumar

Mukherjee

Lloret

2020

IEEE Systems Journal

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Universal-filtered multi-carrier (UFMC) system that is a generalization of filtered orthogonal frequency division multiplexing (OFDM) and filter bank-based multicarrier (FBMC) is being considered as a potential candidate for 5G due to its robustness against inter-carrier interference as in cyclic-prefixbased OFDM systems. However, real-time hardware realization of the multicarrier systems is limited by a large number of arithmetic units for inverse fast Fourier transform (IFFT) and pulse shaping filters. In this paper, we aim to propose a low-complexity and reconfigurable architecture for baseband UFMC transmitter. To the best of our knowledge, the proposed architecture is the first reconfigurable architecture that has the flexibility to choose the number of subcarriers in a subband without any change in hardware resources. In addition, the proposed architecture selects the filter from a group filters with a single selection line. Moreover, we use a commercially available field-programmable gate array (FPGA) device for real-time testing and analyzing the baseband UFMC signal. From the extensive experiments, we study the occupied bandwidth, main-lobe power, and sidelobe power of the baseband signal with different filters in realtime scenarios. Finally, we measure the quantization error in baseband signal generation for the proposed UFMC transmitter architecture and find comparable with the error-bound.

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Section: Cordic Algorithmmentioning

confidence: 99%

Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

Kumar

Mukherjee

Lloret

2020

IEEE Systems Journal

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“…Fast Fourier Transform (FFT) is the most implemented DSP technique in FPGAs, with near to 677 documents related to it. Here, we found CORDIC-based FFT [531][532][533][534][535][536], double-precision floating-point FFT [537], OFDM systems based in FFT [538][539][540][541][542], radix-2 FFT [543,544] and radix-4 FFT [533,[545][546][547] implementations. The Discrete Wavelet Transform (DWT) is a wavelet transform by a certain orthonormal series generated by a discrete wavelet to capture both frequency and location information [548].…”

Section: Digital Signal Processingmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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“…We may note that these two types of windows in (9) and (11) provide the same magnitude with the different phase in the output. Following type-1 sliding window in (8), consider the desired spectrum S p k equal to T1 p k and it can be expanded in the time domain as…”

Section: Triangular Windowed Sdft Algorithmmentioning

confidence: 99%

“…By applying these windows, the main‐lobe width of the spectrum increases, and the side‐lobes get reduced [5]. In the existing literature, there are methods for implementing windows in the time domain [6–8], as well as in the frequency domain [1, 9]. Recently, we have presented an SDFT design integrated with the Hann windowing based on COordinate rotation DIgital computer (CORDIC) algorithm in [10].…”

Section: Introductionmentioning

confidence: 99%

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

Kulshreshtha

Dhar

2019

IET Circuits, Devices & Systems

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This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

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CORDIC-based VLSI architecture for real time implementation of flat top window

Cited by 12 publications

References 24 publications

Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

Field Programmable Gate Array Applications—A Scientometric Review

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

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