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This study presents a COordinate rotation DIgital computer (CORDIC)-based novel architecture combining the sliding discrete Fourier transform (DFT) with Hann windowing to reduce the leakage effect of the DFT spectrum. The proposed architecture also presents a refreshing approach to minimise error due to the finite word-length in the output windowed spectrum compared with the existing method. The architecture can also be extended for other high order generalised cosine windows such as Blackman, Blackman-Harris, and flat-top. The post-route results on the Virtex-6 FPGA as well as the physical ASIC post-layout results are also presented for the proposed architecture.

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A new linear pseudo differential transconductance amplifier (PDTA) has been proposed, which may be operated for the wide range of input signal amplitude with low harmonic distortion. The linearity of the PDTA has been improved using active attenuator. The proposed transconductor circuit shows the total harmonic distortion (THD) of below -62 dB for the input signal of 1 V pp @ 5 MHz. The transconductor is implemented using UMC 180 nm CMOS process with 1.8 V supply voltage at room temperature (27°C).

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.