CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons

Heidarpur, Moslem; Ahmadi, Arash; Ahmadi, M.; Azghadi, Mostafa Rahimi

doi:10.1109/tcsi.2019.2899356

Cited by 97 publications

(65 citation statements)

References 57 publications

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“…The optimized CORDIC operated at 156.937 MHz maximum frequencies with a minimum period of 6.372ns on Spartan-3EFPGA. The proposed optimized CORDIC model is compared concerning previous CORDIC methods like general unrolled CORDIC, Pipelined unrolled, and mux based CORDIC [25] in terms of performance parameters like area (Slice flip-flops, number of slices) and Latency (Number of clock cycles) are tabulated in 4685 mux based CORDIC method, around 4.8 % in slice-FF's, 33.83% in slices, and 12.5% in latency improvements. The above results, the proposed CORDIC is reduced the hardware complexity and improves the performance with area optimization in GMSK systems.…”

Section: Results and Analysismentioning

confidence: 99%

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

Kajur

Prasad²

2020

IJECE

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The Gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.

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Section: Results and Analysismentioning

confidence: 99%

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

Kajur

Prasad²

2020

IJECE

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“…A neuromorphic system can be implemented completely using digital or using a mix of analog and digital CMOS technology . If the system is implemented in digital, the behaviors of neurons and synapses are approximated and the spiking and AER structure of the system is realized in digital architectures .…”

Section: Neuromorphic Systems Designmentioning

confidence: 99%

Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

Azghadi

Chen

Eshraghian

et al. 2020

Advanced Intelligent Systems

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102

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The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

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“…Moreover, the logic capacity of FPGA to implement complex neural algorithms and prototypes without requiring VLSI chip fabrication makes it a brilliant choice. [19][20][21][22][23][24][25][26][27][28][29][30][31] FPGA-based on-chip learning and off-chip learning, which are sometimes known as online learning and offline learning, are the main methods for learning implementation in the hardware at register transfer level (RTL). 26,27 Motivated by these findings, this paper proposes an efficient and high-speed reconfigurable digital implementation of an SNN using Izhikevich neurons and gradient descent learning on an FPGA to approximate the sigmoid function.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

Gholami

Farsa

Karimi

2021

Circuit Theory & Apps

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Hardware implementations of spiking neural networks, which are known as neuromorphic architectures, provide an explicit understanding of brain performance. As a result, biological features of the brain may well inspire the next generation of computers and electronic systems used in such areas as signal processing, image processing, function approximation, and pattern recognition. Approximating nonlinear functions has many uses in computer science and applied mathematics. The sigmoid is the most universal activation function in neural networks by which the relationship between biological and artificial neurons is defined. It is a suitable option for predicting the probability of anything from 0 to 1 as output. In this paper, a spiking neural network using Izhikevich neurons and a gradient descent learning algorithm are propounded to approximate the sigmoid and other nonlinear functions. The flexibility of the spiking network is demonstrated by showing the average relative errors in the approximation process. A time-and cost-efficient digital neuromorphic implementation on the base of on-chip learning method for approximating the sigmoid function is also discussed. The paper reports the results of the hardware synthesis and the spiking network's physical implementation on a field-programmable gate array. The maximum frequency and throughput of the implemented network were 83.209 MHz and 9.86 Mb/s, respectively. K E Y W O R D Sdigital hardware, field-programmable gate array (FPGA), hardware implementation, neuromorphic, on-chip learning, spiking neural networks (SNNs)

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CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons

Cited by 97 publications

References 57 publications

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

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