Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

Azghadi, Mostafa Rahimi; Chen, Ying‐Chen; Eshraghian, Jason K.; Chen, Jia; Lin, Chih-Yang; Amirsoleimani, Amirali; Mehonić, Adnan; Kenyon, Anthony J.; Fowler, Burt; Lee, Jack C.; Chang, Yao‐Feng

doi:10.1002/aisy.201900189

Cited by 102 publications

(60 citation statements)

References 94 publications

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“…[ 134 ] Integration of CMOS and memristive technologies for neuromorphic applications is discussed in the previous study. [ 118 ]…”

Section: Discussionmentioning

confidence: 99%

“…Given such energy concerns, systems based on low‐power memristive devices are a highly promising alternative. [ 117,118 ] Besides having a low carbon footprint, many studies demonstrated devices that mimic neurons, synapses, and plasticity phenomena. Often, such approaches work well for off‐line training.…”

Section: Future Of Neuromorphic and Bio‐inspired Computing Systemsmentioning

confidence: 99%

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Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

Self Cite

197

121

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Three factors are currently driving the main developments in artificial intelligence (AI): availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. Graphics processing units (GPUs) have been demonstrated as effective co-processors for the implementation of machine learning (ML) algorithms based on deep learning (DL). Solutions based on DL and GPU implementations have led to massive improvements in many AI tasks, but have also caused an exponential increase in demand for computing power. Recent analyses show that the demand for computing power has increased by a factor of 300 000 since 2012, and the estimate is that this demand will double every 3.4 months-at a much faster rate than improvements made historically through Moore's scaling (a sevenfold improvement over the same period of time). [1] At the same time, Moore's law has been slowing down significantly for the last few years, [2] as there are strong indications that we will not be able to continue scaling down complementary metal-oxide-semiconductor (CMOS) transistors. This calls for the exploration of alternative technology roadmaps for the development of scalable and efficient AI solutions. Transistor scaling is not the only way to improve computing performance. Architectural innovations, such as GPUs, field-programmable arrays (FPGAs), and application-specific integrated circuits (ASICs), have all significantly advanced the ML field. [3] A common aspect of modern computing architectures for ML is a move away from the classical von-Neumann architecture that physically separates memory and computing. This approach yields a performance bottleneck that is often the main reason for both energy and speed inefficiency of ML implementations on conventional hardware platforms due to

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“…[ 134 ] Integration of CMOS and memristive technologies for neuromorphic applications is discussed in the previous study. [ 118 ]…”

Section: Discussionmentioning

confidence: 99%

Section: Future Of Neuromorphic and Bio‐inspired Computing Systemsmentioning

confidence: 99%

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

Self Cite

197

121

View full text Add to dashboard Cite

show abstract

“…Consider, CMOS‐memristor hybrid hardware and artificial synapses are proposed to perform CNN and DNN operation. [ 182 ]…”

Section: Neuromorphic Computing Systems With Memristorsmentioning

confidence: 99%

Memristive Devices for New Computing Paradigms

Kim

Jang

2020

Advanced Intelligent Systems

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Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

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“…In-memory computing (also called 'processing-in-memory') refers to any effort to process data at the residence of data (i.e., in the memory array) without moving it out to a separate processing unit. 'Processing/computing' could mean a wide variety of operations from arithmetic operations to cognitive tasks like machine learning and pattern recognition [23]. In this review, the focus is on arithmetic operations and how majority logic can enable efficient in-memory computing.…”

Section: Introductionmentioning

confidence: 99%

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Complementary Metal‐Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing

Cited by 102 publications

References 94 publications

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Memristive Devices for New Computing Paradigms

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

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