Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing

Abstract

Conventional test access mechanism (TAM) and test wrappers of complex System-on-Chip (SoC) designs do not adequately utilize the system resources available in the functional mode of operation. With the advent of Network-on-Chip (NoC), the internal data transaction bandwidth has risen dramatically. This increase does not automatically translate to benefits during test. In this paper, we present a core test wrapper which takes advantages of the functional interconnect bandwidth to improve test application efficiency. Experimental results clearly demonstrate the benefit of the proposed approach in improving test application time.