Core tunneling: Variation-aware voltage noise mitigation in GPUs

Thomas, Renji; Barber, Kristin; Sedaghati, Naser; Zhou, Li; Teodorescu, Radu

doi:10.1109/hpca.2016.7446061

Cited by 23 publications

(4 citation statements)

References 34 publications

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“…To evaluate the impact of GPU Stacking to compensate for the performance loss due to PV, we model PV following an existing methodology [37]. Briefly, VARIUS-NTV [4] (planar) and VARIUS-TC [38] (FinFET) are used to generate process variation maps.…”

Section: B Process Variation Modelingmentioning

confidence: 99%

“…In short, a off-chip and on-chip power delivery network is simulated with cores modeled as current-controlled current sources, where the transient current is estimated by cycle-accurate micro-architectural simulation for each core. This type of approach has been used in multiple studies of this sort [40], [37], [41]. Thus, we use the power traces from ESESC for each lane.…”

Section: Power Delivery Simulation and Technology Nodementioning

confidence: 99%

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GPU NTC Process Variation Compensation With Voltage Stacking

Possignolo

Ebrahimi

Ardestani

et al. 2018

IEEE Trans. VLSI Syst.

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Near Threshold Computing (NTC) has the potential to significantly improve efficiency in high throughput architectures like GPGPUs. Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU Stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU Stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without process variation management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-process variation case, delivering on average (across chips) ≈ 80% of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ≈ 50% of the nominal performance. We also show that our approach can be applied on top of multi-frequency domain designs, improving the overall performance.

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Section: B Process Variation Modelingmentioning

confidence: 99%

Section: Power Delivery Simulation and Technology Nodementioning

confidence: 99%

GPU NTC Process Variation Compensation With Voltage Stacking

Possignolo

Ebrahimi

Ardestani

et al. 2018

IEEE Trans. VLSI Syst.

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“…Various works focus on improving the processor PDN using various techniques (e.g., thermal-aware voltage regulators (VRs) [72], re-con gurable PDN [32], VR phase scaling [11], VR e ciency-aware power management [12], on-chip VRs for fast DVFS [53,73,137], voltage stacking [33,90,142], PDNs for waferscale processors [90], voltage noise reduction [16,35,36,44,74,84,95,96,108,119], voltage noise modeling [141,143], multiple voltage domains [100,138], voltage optimizations [115], and adaptive DVFS [22,91]). These works focus on adapting power management techniques that already exist in modern client processors (such as voltage noise reduction and modeling, power management techniques that optimize VR e ciency, using fast VRs for better DVFS, utilizing on-chip VRs for building multiple voltage domains to improve energy-e ciency), but they do not alleviate the inherent energy ine ciencies of commonly-used PDNs in client processors due to operating across a wide range of power and wide variety of workloads.…”

Section: Introductionmentioning

confidence: 99%

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

Haj-Yahya¹,

Alser²,

Kim³

et al. 2020

Preprint

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Modern client processors typically use one of three commonlyused power delivery network (PDN) architectures: 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), and 3) low dropout voltage regulators (LDO). We observe that the energy-e ciency of each of these PDNs varies with the processor power (e.g., thermal design power (TDP) and dynamic power-state) and workload characteristics (e.g., workload type and computational intensity). This leads to energyine ciency and performance loss, as modern client processors operate across a wide spectrum of power consumption and execute a wide variety of workloads.To address this ine ciency, we propose FlexWatts, a hybrid adaptive PDN for modern client processors whose goal is to provide high energy-e ciency across the processor's wide range of power consumption and workloads. FlexWatts provides high energy-e ciency by intelligently and dynamically allocating PDNs to processor domains depending on the processor's power consumption and workload. FlexWatts is based on three key ideas. First, FlexWatts combines IVRs and LDOs in a novel way to share multiple on-chip and o -chip resources and thus reduce cost, as well as board and die area overheads. This hybrid PDN is allocated for processor domains with a wide power consumption range (e.g., CPU cores and graphics engines) and it dynamically switches between two modes: IVR-Mode and LDO-Mode, depending on the power consumption. Second, for all other processor domains (that have a low and narrow power range, e.g., the IO domain), FlexWatts statically allocates o -chip VRs, which have high energy-e ciency for low and narrow power ranges. Third, FlexWatts introduces a novel prediction algorithm that automatically switches the hybrid PDN to the mode (IVR-Mode or LDO-Mode) that is the most bene cial based on processor power consumption and workload characteristics.

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“…• GPUs: Aggressive undervolting is also considered as a promising energy efficiency improvement technique in GPUs [158], [159]. As an example of commercial GPUs, [155] studied this approach in GPU register files and proposed…”

Section: Aggressive Undervolting Into the Critical Voltage Regionsmentioning

confidence: 99%

Aggressive undervolting of FPGAs : power & reliability trade-offs

Salami¹

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In this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip vendors to ensure the worst-case process and environmental scenarios. Through experimenting on several FPGA architectures, we con¿rm a large voltage guardband for several FPGA components, which in turn, delivers signi¿cant power savings. However, further undervolting below the voltage guardband may cause reliability issues as the result of the circuit delay increase, and faults might start to appear. We extensively characterize the behavior of these faults in terms of the rate, location, type, as well as sensitivity to environmental temperature, primarily focusing on FPGA on-chip memories, or Block RAMs (BRAMs). Understanding this behavior can allow to deploy ef¿cient mitigation techniques, and in turn, FPGA-based designs can be improved for better energy, reliability, and performance trade-offs. Finally, as a case study, we evaluate a typical FPGA-based Neural Network (NN) accelerator when the FPGA voltage is underscaled. In consequence, the substantial NN energy savings come with the cost of NN accuracy loss. To attain power savings without NN accuracy loss below the voltage guardband gap, we proposed an application-aware technique and we also, evaluated the built-in Error-Correcting Code (ECC) mechanism. Hence, First, we developed an application-dependent BRAMs placement technique that relies on the deterministic behavior of undervolting faults, and mitigates these faults by mapping the most reliability sensitive NN parameters to BRAM blocks that are relatively more resistant to undervolting faults. Second, as a more general technique, we applied the built-in ECC of BRAMs and observed a signi¿cant fault coverage capability thanks to the behavior of undervolting faults, with a negligible power consumption overhead. En este trabajo, evaluamos el reducir el voltaje en forma agresiva, es decir, bajar la tensión por debajo del nivel nominal para reducir el consumo de energía en Field Programmable Gate Arrays (FPGA). Por lo general, los vendedores de chips establecen margen de seguridad al voltaje para garantizar el funcionamiento de los mismos en el peor de los casos y en los peores escenarios ambientales. Mediante la experimentación en varias arquitecturas FPGA, confirmamos que hay un margen de seguridad de voltaje grande en varios de los componentes de la FPGA, que a su vez, nos ofrece ahorros de energía significativos. Sin embargo, un trabajar a un voltaje por debajo del margen de seguridad del voltaje puede causar problemas de confiabilidad a medida ya que aumenta el retardo del circuito y pueden comenzar a aparecer fallos. Caracterizamos ampliamente el comportamiento de estos fallos en términos de velocidad, ubicación, tipo, así como la sensibilidad a la temperatura ambiental, centrándonos principalmente en memorias internas de la FPGA, o Block RAM (BRAM). Comprender este comportamiento puede permitir el desarrollo de técnicas eficientes de mitigación y, a su vez, mejorar los diseños basados en FPGA para obtener ahorros en energía, una mayor confiabilidad y un mayor rendimiento. Finalmente, como caso de estudio, evaluamos un acelerador típico de Redes Neuronales basado en FPGA cuando el voltaje de la FPGA esta por debajo del nivel mínimo de seguridad. En consecuencia, los considerables ahorros de energía de la red neuronal vienen asociados con la pérdida de precisión de la red neuronal. Para obtener ahorros de energía sin una pérdida de precisión en la red neuronal por debajo del margen de seguridad del voltaje, proponemos una técnica que tiene en cuenta la aplicación, asi mismo, evaluamos el mecanismo integrado en las BRAMs de Error Correction Code (ECC). Por lo tanto, en primer lugar, desarrollamos una técnica de colocación de BRAM dependiente de la aplicación que se basa en el comportamiento determinista de las fallos cuando la FPGA funciona por debajo del margen de seguridad, y se mitigan estos fallos asignando los parámetros de la red neuronal más sensibles a producir fallos a los bloques BRAM que son relativamente más resistentes a los fallos. En segundo lugar, como técnica más general, aplicamos el ECC incorporado de los BRAM y observamos una capacidad de cobertura de fallos significativo gracias a las características de comportamiento de fallos, con una sobrecoste de consumo de energía insignificante

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Core tunneling: Variation-aware voltage noise mitigation in GPUs

Cited by 23 publications

References 34 publications

GPU NTC Process Variation Compensation With Voltage Stacking

GPU NTC Process Variation Compensation With Voltage Stacking

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

Aggressive undervolting of FPGAs : power & reliability trade-offs

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