Correlated noise in bipolar transistors: Model implementation issues

Huszka, Z.; Chakravorty, Anjan

doi:10.1016/j.sse.2015.07.004

Cited by 2 publications

(2 citation statements)

References 36 publications

(65 reference statements)

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“…To evaluate this noise contribution a generator has been added between the gate and the source, in order to generate a signal which is a linear combination of two other white noise signals. [23][24][25] The simulation result is shown represented in Fig. 7.…”

Section: Analysis and Discussion Of Cntfet Noise Simulationsmentioning

confidence: 99%

A Compact Noise Model for C-CNTFETs

Marani

Gelao

Perri

2017

ECS J. Solid State Sci. Technol.

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In this paper we present a compact noise model for C-CNTFETs implemented in Verilog-A. After a brief description of the main noise sources existing in CNTFETs, which constitute a significant limitation in the design of analogue and logic CNTFETs circuits, we enhance a model, already proposed by us, considering the noise sources. The simulation results allow to determine easily the different noise contributions and the noise figure. At last the proposed noise model is compared with the Landauer model, obtaining results comparable but with an improvement in terms of run time.

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Section: Analysis and Discussion Of Cntfet Noise Simulationsmentioning

confidence: 99%

A Compact Noise Model for C-CNTFETs

Marani

Gelao

Perri

2017

ECS J. Solid State Sci. Technol.

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“…For implementing i D1 and t 21 i D1 of (15), a single-node subcircuit is needed. This single-node implementation is comparable with the one obtained in [21] by using an extended orthogonalization scheme. From (1), we observe that the noise models depend on the underlying expressions of y-parameters, i.e., the smallsignal NQS models.…”

Section: B Model Implementationmentioning

confidence: 52%

Graded Applications of NQS Theory for Modeling Correlated Noise in SiGe HBTs

Kumar

Chakravorty

Fischer

et al. 2015

IEEE Trans. Electron Devices

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In this paper, we develop a correlated noise model for bipolar transistors from an accurate nonquasi-static model. The proposed noise model includes the signal delay through base-collector space-charge region and is implemented using four extra nodes. We also present a simplified version of the same model that requires only two extra nodes. A further simplified version that uses only one extra node is found to be identical with a state-of-the-art correlated noise model. When compared with the device simulation data, our proposed models show improved accuracy compared with the existing state-of-the-art noise models.

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Correlated noise in bipolar transistors: Model implementation issues

Cited by 2 publications

References 36 publications

A Compact Noise Model for C-CNTFETs

A Compact Noise Model for C-CNTFETs

Graded Applications of NQS Theory for Modeling Correlated Noise in SiGe HBTs

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