Correlation between low-frequency noise and low-temperature performance of two-dimensional electron gas FET's

Si vertical JFET at low temperatures ; I-V characteristics and low frequency noise

“…The spectral density fbnction Sv(f) was measured at 300K and 77K at frequencies, f, in the range 250Hz< f< 100kHz. The experimental set-up has been described elsewhere [6]. The noise is expressed in terms of the voltage generated by the equivalent source placed at the input, with the gate load of 50Q.…”

Mixed-mode simulation of DX trap-induced slow transient effects on AlGaAs/GaAs HEMT inverters

“…It should be emphasized that they are both time-and x-direction dependent. In other words, we need to solve (2) and (4) to generate the relationship between the channel electron contribution and the gate-to-channel potential at each cross section of a device and at each time step. An assumption of a constant quasi-Fermi level in the perpendicular direction is adopted to deduce bulk electron concentrations in the conduction band and in the shallow donor states in the AlGaAs layer.…”

“…An assumption of a constant quasi-Fermi level in the perpendicular direction is adopted to deduce bulk electron concentrations in the conduction band and in the shallow donor states in the AlGaAs layer. These values are used in (4) and also in the DX rate equation again at the next time step. In the calculation of the drain current, a simple two-region Grebene-Ghandhi model [ 151 is utilized to manifest the slow transient effects.…”

“…However, there has been increasing concern that deep traps in the Si-doped Al,Ga, -,As layer, commonly known as DX centers, may play a crucial role in the performance degradation of HEMT devices and circuits. The major detrimental effects include low-temperature current collapse [ 3 ] , low-frequency noise [4], device threshold voltage shifts [ 5 ] , [6], and remarkable slow current transients when a device is subject to a gate or a drain voltage pulse [6]- [8]. Recently, it has been reported that the trapinduced transient effects may result in a significant variation of the output pulsewidth in a string of direct-coupled FET logic (DCFL) inverters [9], [lo].…”

Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters

“…INTRODUCTION HE EXISTENCE of DX traps in the Si-doped T A 1 , G a -,As layer is widely known to be the origin of performance degradation in A1,GaI -,As /GaAs HEMT devices and circuits. The major detrimental effects include low temperature current collapse [ 11, low frequency noise [2], device threshold voltage shift [3] and remarkable "slow" current transients when a device is subject to a gate or drain voltage pulse [4]. Previous experimental study has also shown that deep traps may result in the hysteretic characteristics in the input-output voltage transfer function and a significant variation of the output pulse width in a string of direct coupled FET logic (DCFL) inverters [5].…”