Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

Chidambaram, P.R.; Gan, Chee Lip; Sengupta, Shubhalakshmi; Ge, Lixin; Chen, Y.; Yang, Shu Ching; Liu, P.; Wang, J.; Yang, Ming‐Ta; Teng, Charles; Du, Yi; Patel, P.; Kamal, Pratyush; Bucki, Robert; Vang, F.; Datta, Animesh; Bellur, K.; Yoon, Sei Seung; Chen, N.; Thean, Aaron; Han, Michael; Terzioglu, E.; Zhang, X.; Fischer, Jeff; Sani, M.; Flederbach, B.; Yeap, Geoffrey

doi:10.1109/iedm.2010.5703432

Cited by 11 publications

(4 citation statements)

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“…With cost and power centric circuit/device/process cooptimization, this versatile low cost technology has demonstrated the capability of supporting a wide range of mobile applications. 28LP not only enabled quicker time-to-market with a less risky technology choice at the time, but was also capable of delivering high-end quad-core mobile processors up to 1.9GHz with rigorous optimization [4]. The more recent 28nm high-k metal gate technology offered high-k metal gate with strong strain engineering while optimizing metal stack is well suited for the high speed tablet/high-end smartphone market.…”

Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 94%

“…High density design style that produces larger process/device variation is allowed in low frequency blocks based on analysis of yield risk and benefit to design. High density blocks in Qualcomm 28LP product achieved a record gate density of 4400 KG/mm², about 2.5× increase from the previous node [4]. It is worth noting that technology definition must consider the ultimate end-product needs as well as the time-to-market constraint, in addition to the traditional node scaling target.…”

Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 99%

“…A balanced approach is needed to deliver the best value in terms of Cost/Power/Area/Performance for the mobile SoC design. RDRs have been applied in mobile SoC design since 45nm node to optimize density/power/performance [4]. Design rules tailored for high density design, high performance logic design, and high performance analog and I/O design can be applied to the corresponding components in the same mobile SoC chip to achieve best area/performance optimization under a given technology offering (Table 1).…”

Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 99%

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Technology-design-manufacturing co-optimization for advanced mobile SoCs

et al. 2014

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How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

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Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 94%

Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 99%

Section: Design For Manufacturability and Restrictive Design Rulesmentioning

confidence: 99%

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Technology-design-manufacturing co-optimization for advanced mobile SoCs

et al. 2014

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“…VDR is a strong function of circuit topology and physical layout implementation. Latest generation of mobile SoCs in 28nm [1] has millions of flop. Table I lists number of different Vth flops in couple latest generation of mobile chipsets.…”

Section: Introductionmentioning

confidence: 99%

Experiments and analysis to characterize logic state retention limitations in 28nm process node

Dasnurkar

Datta

Abu-Rahma

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multitasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low voltage data-retention failure mechanism in flops. It analyzes the impact of design and process parameters on the data retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

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Characterization of SRAM Sense Amplifier Input Offset for Yield Prediction

Abu-Rahma

Anis

2012

Nanometer Variation-Tolerant SRAM

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Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

Cited by 11 publications

References 0 publications

Technology-design-manufacturing co-optimization for advanced mobile SoCs

Technology-design-manufacturing co-optimization for advanced mobile SoCs

Experiments and analysis to characterize logic state retention limitations in 28nm process node

Characterization of SRAM Sense Amplifier Input Offset for Yield Prediction

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