Cost-effective numerical simulation of SEU

Spatially-resolved picosecond laser induced transients have been measured in a 0.18 m CMOS inverter test structure as a function of temperature. Sensitive -drain and -drain nodes have been scaled in size to accommodate characteristic differences between ion and laser tracks. Images based on pulse characteristics have been collected from 325 K to 400 K and transient currents extracted from laser strikes to both the OFF drain and its surroundings. With increasing temperature strikes to the OFF drain result in a pulse width which appears to broadens whilst the charge collected surprisingly decreases.

Section: A Device Under Testmentioning

confidence: 99%

Temperature Dependence of Spatially Resolved Picosecond Laser Induced Transients in a Deep Submicron CMOS Inverter

Laird

Yuan

et al. 2009

“…Scaling schemes have been proposed that adjust the Auger recombination rate in an attempt to correct for geometry effects [129]. Another method is to use quasi-3-D versions of the popular PISCES-II code, based on cylindrical symmetry and coordinate transformations [134]. Many charge collection and SEU studies have been performed using these modified 2-D codes [53], [135]- [138].…”

Section: B Multidimensional Device Simulationsmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

904

427

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

“…Although PISCES is only capable of simulating two-dimensional structures, it is possible to obtain quasi-3D simulations by assuming cylindrical symmetry and restricting the ion strike location to the origin. This approach has been widely used in the past [9], and provides a far less costly and less time consuming approach than full 3-D simulations [10][11][12][13]. We used this geometrical simplification to model the linear transistors in this work.…”

Section: A Transistor Typesmentioning

confidence: 99%

A model for single-event transients in comparators

Johnston

Swift

Miyahira

et al. 2000

A two-step modeling approach is developed for single-event transients in linear circuits that uses the PISCES device simulation program to calculate transient currents in key internal transistor structures. Those currents are then applied at the circuit level using the SPICE circuit analysis program. The results explain the dependence of transients on input differential voltage, as well as the dependence of transient signals on output loading conditions. Error rate predictions based on laboratory testing and modeling are in close agreement with the observed number of "trips" in comparators within power control modules that have operated in a deep space environment for nearly three years.