Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

Bleiker, Simon J.; Taklo, Maaike M. Visser; Lietaer, Nicolas; Vogl, Andreas; Bakke, Thor; Niklaus, Frank

doi:10.3390/mi7100192

Cited by 13 publications

(4 citation statements)

References 24 publications

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“…(2) adopting buried conductors created by diffusion under a layer of epitaxial silicon to avoid the height difference in the anodic bonding [6]; (3) using the thick solder (or polymer) layer to compensate height differences between metal lines and bonding rings in the solder [7] (or polymer [8]) bonding. However, choosing a thick Au layer not only requires a complex electroplating process but also instead results in the serious delamination effect at bonding rings for Au-Si bonding [9].…”

Section: Introductionmentioning

confidence: 99%

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Liang

Liu

Xiong

2019

J. Micromech. Microeng.

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Driven by ever-growing demands on 3D integration, various state-of-the-art electronics packaging techniques have been developed. This study presents a novel and cost-efficient 3D wafer level packaging technology based on co-planar Au–Si bonding structures, whose two remarkable features are (1) eliminating the height difference derived from multi-layer metal interconnection lines crossing bonding rings by building co-planar bonding structures and (2) accomplishing vertical interconnections of low-resistivity Si column structures by forming Au–Si bonding ohmic contacts. In this paper, the packaging structure is interpreted by designs, fabrications and tests, in which the efficiency verification on co-planar bonding structures and vertical interconnections is concretely addressed. The performances on co-planar bonding structures have been revealed by 3D profiles of bonding surfaces, cross-sectional SEM images (the gap-free bonding layer) and tensile tests for Au–Si bonding strength. Besides, tests on leak rates of packaged chips indicate good packaging hermeticity. In terms of vertical interconnection properties, an in situ extracting method on the specific contact resistance (ρc) is also introduced to quantitatively appraise the quality of Au–Si ohmic contacts. Therefrom, the measured resistance of a vertical interconnection (~1 Ω) could be qualified for most devices’ interconnection requirements. And further, the extracted ρc values of 1.83–3.48 × 10−8 Ω · m2 also imply forming of good ohmic contacts in Au–Si bonding. More importantly, being analogously conducted by any available eutectic bonding techniques, this 3D packaging method has inherently extensive application prospects.

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Section: Introductionmentioning

confidence: 99%

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Liang

Liu

Xiong

2019

J. Micromech. Microeng.

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“…To avoid bouncing back, the over-damping condition of RF MEMS switches is required in device packages and thus can be realized by regulating the cap cavity depth. (8) In addition, it is identified that MEMS resonators' quality factors of packaged ones (under atmospheric pressure) are smaller than those of unpackaged ones owing to squeeze film damping from cap and substrate cavities, (9) which is similarly reported in studies on MEMS switches (10) and energy harvesters. (11,12) Also, some studies indicate that the squeeze film damping coefficient of MEMS resonators decreases with increasing cavity depth, e.g., in the MEMS rotary motors (13) and scanners.…”

Section: Introductionmentioning

confidence: 65%

Cavity-Depth Effect on 3D Wafer-Level-Packaged MEMS Resonators by Slide-Film Damping

Liang,

Lv,

Han

et al. 2024

Sensors and Materials

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The slide-film damping effect caused by cavity structures is easily neglected in the design of bulk-micro-machined resonant MEMS device fabrication and packaging processes. On the basis of theory calculations, simulations, and actual tests, in this study, we investigate the cavity-depth effect on 3D wafer-level packaged MEMS resonators with the in-plane-motion mode, in which slide-film damping is dominant. On the one hand, it is found that the slide-film damping coefficient is inversely proportional to the cavity depth and remains stable for the cavity depth above a specific value. The critical cavity depth acquired from theoretical results is ~10 μm, which is distinct from that of ~30 μm from simulation results. On the other hand, the variation tendency of simulation results is more in agreement with those of test results for fabricated devices than the theoretical prediction. Hence, before the structure fabrication for a resonator dominated by slide-film damping, it is imperative to choose a conservative cavity depth with a relatively high value from the combination of theory and simulation analyses, so as to ensure the high or desired Q-factors of fabricated resonators, particularly in wafer-level packaging with the low-vacuum or atmospheric pressure. Overall, this work provides not only an analysis strategy on device cavities' slide-film damping but also the optimization design of wafer-level packaging structures and processes.

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“…Therefore, the package must offer encapsulation with a low gas leak rate in an inert ambient gas, such as nitrogen, at atmospheric pressure to ensure the long-term stability and reliability of the MEMS switches. To solve these problems, the packaging is preferably implemented on a wafer level prior to die singulation, which is known as the wafer-level package method [ 6 , 7 ].…”

Section: Introductionmentioning

confidence: 99%

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

2018

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A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold) layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW) lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

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Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

Cited by 13 publications

References 24 publications

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Cavity-Depth Effect on 3D Wafer-Level-Packaged MEMS Resonators by Slide-Film Damping

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

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