Cost-performance wafer thinning technology

Wu, L.; Chan, James W.; Hsiao, C.S.

doi:10.1109/ectc.2003.1216488

Cited by 18 publications

(12 citation statements)

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“…[1], [2], [3], [4] These are Wet etching, Dry polishing, Plasma etching and CMP (Chemical Mechanical Polishing) as mirror finishing methods.…”

Section: Fig2 Process Flowmentioning

confidence: 99%

“…Several studies have been conducted on wafer thinning processes. [1], [2], [3], [4] Chip strength is markedly decreased by mechanical defects and micro cracks, because a semiconductor chip is made of silicon, which is a brittle material. Therefore, the manufacture of thin chips must meet the requirement of no damage on the entire chip surface.…”

Section: Problems In Thinning Chipsmentioning

confidence: 99%

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The development of Cleaving — DBG + CMP process

Takyu

Kiritani

Kurosawa

et al. 2010

2010 IEEE CPMT Symposium Japan

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As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thicknesses of 50 to 200 µm, such damage has to be avoided.In this study, novel manufacturing process steps for thin semiconductor devices are followed.

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“…[1], [2], [3], [4] These are Wet etching, Dry polishing, Plasma etching and CMP (Chemical Mechanical Polishing) as mirror finishing methods.…”

Section: Fig2 Process Flowmentioning

confidence: 99%

Section: Problems In Thinning Chipsmentioning

confidence: 99%

The development of Cleaving — DBG + CMP process

Takyu

Kiritani

Kurosawa

et al. 2010

2010 IEEE CPMT Symposium Japan

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“…The damage layer on the wafer backside after backgrinding causes wafer strength decrease, wafer warpage, and will subsequently affect the mechanical integrity of the die. 9,[12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]59 This has necessitated a post-grinding treatment process to remove the wafer backside damage and residual stresses, especially for wafers below 100 mm thickness. Several post-grinding treatment were developed for this purpose: chemical mechanical polishing (CMP), 9,[12][13][14][15][16]19,20,25,[27][28][29][30][31]111,128 wet chemical etching, 9,12,13,16,18,19,25,27,34,35,89,90,111,114 plasma etching, …”

Section: Introductionmentioning

confidence: 99%

Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review

Marks

Hassan

Cheong

2015

Critical Reviews in Solid State and Materials Sciences

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Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 mm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.

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“…In spite of its removal of backside saw marks by etching, condition (2) is not different from condition (1). Moreover, in spite of remaining backside saw marks, the chip strength under condition (3) is greater than that under condition (2). Accordingly, backside chipping has a larger influence than backside saw marks on chip strength.…”

Section: Condition (1) Dicing After Backside Grinding Condition (2) Dmentioning

confidence: 55%

“…1 shows a chip damage caused by BSG and dicing processes and its size such damage is not so much of a problem in thick chips however, it causes wafer breakage or chip cracking in thin chips during thinning, wafer transportation and the subsequent process steps, such as die bonding, wire bonding, and package reliability test. Several studies have been conducted on wafer thinning processes [1], [2]. The following ideas are suggested to prevent wafer breakage in wafer transportation.…”

Section: Problems In Thinning Chipsmentioning

confidence: 99%