Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran, Ramon; González, Marc; Martorell, Xavier; Navarro, Nacho; Ayguadé, Eduard

doi:10.1093/comjnl/bxs116

Cited by 25 publications

(25 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Power models based on performance counters could be classified into two main categories [4]: 1) Top-down counterbased modeling method, which uses only a few hardware devices to build a system-level power model; 2) Bottom-up counter-based modeling method, which collects as much as information from massive hardware event training and thus plenty of power-related factors could be gathered in order to reflect the estimated value of the applications. McCullough et al [5] evaluated the need for pervasive power instrumentation by exploring the effectiveness of power modeling on modern hardware.Joseph et al [6] examined the use of hardware performance counters as proxies for power meters and discussed which performance counters count power-relevant events.…”

Section: Related Workmentioning

confidence: 99%

Modeling the Power Consumption of Multiple Typical Applications Based on Linux

Wang¹,

Li²,

Zhang³

et al. 2016

Proceedings of the 2016 International Conference on Communications, Information Management and Network Security

View full text Add to dashboard Cite

Abstract-Since huge power consumption of large data centers has become a crucial problem recently, power models, especially precise models, turn out to be important for service providers to learn about the application status in order to make wise decisions. In this paper, we focus on the power modeling of typical applications upon Linux platforms, including CPU-intensive applications, memory-intensive applications, and networkintensive applications. We established models for these different types of applications respectively based on the collection of massive realistic data and further calibrated these models. Error analysis was also given after comparing the computed values with the actual measured data. Finally, synthetic model for the hybrid application execution scenario was figured out and discussed.

show abstract

Section: Related Workmentioning

confidence: 99%

Modeling the Power Consumption of Multiple Typical Applications Based on Linux

Wang¹,

Li²,

Zhang³

et al. 2016

Proceedings of the 2016 International Conference on Communications, Information Management and Network Security

View full text Add to dashboard Cite

show abstract

“…The PMC-based modelling [34] is implemented either with top-down or bottom-up approaches. The first do not depend on modelled architecture thus enabling a fast and an easy deployment [35], while the second depends on the underlying architecture and is therefore able to produce more informative, responsive and accurate power/energy models.…”

Section: Energy Measurement and Profilingmentioning

confidence: 99%

Energy Efficiency of Parallel Multicore Programs

Davidović¹,

Depolli²,

Lipić³

et al. 2016

SCPE

View full text Add to dashboard Cite

Abstract. The increasing energy consumption of large-scale high performance resources raises technical and economical concerns. A reduction of consumed energy in multicore systems is possible to some extent with an optimized usage of computing and memory resources that is tailored to specific HPC applications. The essential step towards more sustainable consumption of energy is its reliable measurements for each component of the system and selection of optimally configured resources for specific applications. This paper briefly surveys the current approaches for measuring and profiling power consumption in large scale systems. Then, a practical case study of a real-time power measurement of multicore computing system is presented on two real HPC applications: maximum clique algorithm and numerical weather prediction model. We assume that the computing resources are allocated in a HPC cloud on a pay-per-use basis. The measurements demonstrate that the minimal energy is consumed when all available cores (up to the scaling limit for a particular application) are used on their maximal frequencies and with threads binded to the cores.Key words: Energy efficiency, high-performance, maximum clique, numerical weather prediction AMS subject classifications. 65Y05, 68U201. Introduction. Nowadays, a large number of hard problems is being solved efficiently on large-scale computing systems such as clusters, grids and clouds. The main building blocks of such systems are highperformance computing (HPC) clusters, since they are furthermore embedded both into grid computing systems as well as cloud computing systems [1]. A great advantage of Graphical Processor Unit (GPU) accelerators over multicore platforms was demonstrated in terms of energy efficiency [2] with an overall energy consumption for an order of magnitude smaller for the GPUs. Inside the clusters, the many-core architectures, such as GPUs [3], as well as even more specialized data-flow computers [4] are getting an increasingly large supporting role but the main processing is still performed by the multi-core main processors because of simple programming model.In this research, we analyze the energy consumption profile of the processors on a two processor multi-core computer, while varying its workload.With the increasing number of components in large-scale computing systems the energy consumption is steeply increasing [5]. In computer systems, energy (measured in Joules) is represented as the electricity resource that can power the hardware components to do computation. On the other hand, power is the amount of energy consumed per unit time (measured in Joules per second or Watts). The ever-increasing energy consumption of large-scale computing systems causes higher operation costs (e.g. electricity bills) and has negative environmental impacts (e.g. carbon dioxide emissions). Therefore, when designing large-scale computing systems, the focus is often shifting from performance improvements to energy efficiency.Energy can be reduced at several levels of the distrib...

show abstract

“…Counter-based power models have not only been used to model the power consumption of the processor [5,29,35,43], they also have been useful to predict the consumption of the rest of the components in the system [10,11]. In particular, bottom-up counter-based power modeling methodologies have been shown to be a competitive approach [7]. Besides accuracy and generality [8,9], these types of models provide a finegrained granularity, sometimes allowing per functional unit breakdowns [27].…”

Section: Bottom-up Cmp/smt Aware Counter-based Processor Power Modelmentioning

confidence: 99%

“…In [27], a bottom-up power model of a Pentium 4 is presented. In [7][8][9], the authors model a dual-core processor without SMT. In contrast, we model a highly parallel processor such as the POWER7, with 8 cores and up to 4-way SMT capabilities.…”

Section: Bottom-up Cmp/smt Aware Counter-based Processor Power Modelmentioning

confidence: 99%

“…To the best of our knowledge, this is the first bottom-up counter-based power model for a CMP/SMT processor. This type of models are known to perform better [7][8][9] than those derived from common modeling approaches. However, they had limited applicability due to the lack of frameworks for automating the generation of the micro-architecture aware training data that they need.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as maxpower stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications).

show abstract

Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Cited by 25 publications

References 46 publications

Modeling the Power Consumption of Multiple Typical Applications Based on Linux

Modeling the Power Consumption of Multiple Typical Applications Based on Linux

Energy Efficiency of Parallel Multicore Programs

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Contact Info

Product

Resources

About