Counteracting differential power analysis: Hiding encrypted data from circuit cells

Abstract

We propose a balanced Pre-Charge Static Logic (PCSL) circuit style for asynchronous systems, and compare it against other reported circuit styles to counteract differential power analysis (DPA). Our study shows that all these circuit styles (including our balanced PCSL) dissipate different energy due to data-dependency, and hence balancing the energy of circuits embodying these circuit styles remains challenging. However, in view of low circuit overheads and asynchronous operations (with noise generation), our balanced PCSL is still competitive in terms of DPA-resistance, requiring 3.5× less power traces than its NULL convention logic counterpart.

Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks

“…It is necessary to state that the goal of this work is not to perform a comparative study between these countermeasures. Thus, the topologies were chosen to include a wide-ranging of approaches, as follows: SABL, which is the pioneer logic style to apply the DPL method to design DPAresistant circuits [7]; WDDL, whose logic cells are designed using standard-cell libraries [8]; PCSL, which introduces redundant transistors to balance internal capacitance [9]; and iDDPL, which employs the TDPL procedure [10].…”

“…Several DPA-resistant topologies adopting the DPL technique have been proposed. Examples of these include the Sense Amplifier Based Logic (SABL) [7], the Wave Dynamic Differential Logic (WDDL) [8], and the Pre-Charge Static Logic (PCSL) [9]. Additionally, recently published topologies as the Improved Delay-based Differential Pre-charge Logic (iDDPL) [10] and the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL) [11] are designed with a three-phase dual-rail pre-charge logic (TDPL).…”

High Secured Low Power Multiplexer-LUT Based AES S-Box Implementation

“…In another perspective, S-Box dissipates the most power [3] and easily leak out the information of the processed intermediate data through CPA attack. Numerous literatures have reported to protect S-Box against CPA attack [2]- [4] and [5]. A Random of Dynamic Voltage Scaling (RDVS) design was reported in [4].…”

A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation

“…The current equalizer implemented with integrated switching capacitors, which isolates the encryption circuits activity by equalizing the current. However, it is 33% power overhead 2× slower than conventional differential logic [8]. The iSCE is an improvement of the SCCE performance, which is only at the vulnerable round of AES-128 (i.e.…”

“…In the cell level, several techniques have been reported such as Sense Amplifier Based Logic (SABL) [5], Wave Dynamic Differential Logic (WDDL) [6], Three-phase Dual-rail Pre-charge Logic (TDPL) [7] and Pre-Charge Static Logic (PCSL) [8]. The concept of SABL is to balance internal charges by fully charging and discharging all internal node for different processed data (i.e.…”