2021
DOI: 10.1049/cdt2.12027
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Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

Abstract: The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short-period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider-based pseudorandom bit generator is compared with other LCG-based realisations, showing great improvement. First,… Show more

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Cited by 10 publications
(1 citation statement)
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“…A digital comparator circuit should therefore be carefully optimized for fast and efficient electronic system development. The use of a binary comparator circuit is also observed in the arithmetic components of a random number generator (RNG) [3,4], digital signal processor (DSP), application-oriented proces-sors such as media processors [5], vision processors [2], etc.…”
Section: Introductionmentioning
confidence: 99%
“…A digital comparator circuit should therefore be carefully optimized for fast and efficient electronic system development. The use of a binary comparator circuit is also observed in the arithmetic components of a random number generator (RNG) [3,4], digital signal processor (DSP), application-oriented proces-sors such as media processors [5], vision processors [2], etc.…”
Section: Introductionmentioning
confidence: 99%