Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

Abstract

This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a processldevice simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented.

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

“…However, they are not directly linked to circuit performance. A methodology that accounts for all statistical disturbances inherent in the process and preserves all correlations is based on coupling of statistical process simulation, device and circuit simulation [5]. We have developed such a system.…”