Coverage metrics for functional validation of hardware designs

Tasiran, Serdar; Keutzer, Kurt

doi:10.1109/54.936247

Cited by 180 publications

(104 citation statements)

References 27 publications

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“…A coverage item c ∈ C is a single condition. The form of these conditions is defined by C. Two typical coverage metrics used in hardware design are statement coverage and toggle coverage [TK01]. Toggle coverage is a coverage metric especially for hardware design, on the other hand statement coverage is also used in software design [JHS01].…”

Section: Preliminariesmentioning

confidence: 99%

Automated feature localization for hardware designs using coverage metrics

Malburg

Finder

Fey

2012

Proceedings of the 49th Annual Design Automation Conference

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Due to the increasing complexity modern System on Chip designs are developed by large design teams. In addition, existing design blocks are re-used such that the knowledge about these parts of the design entirely depends on the quality of the documentation. For a single designer it is almost impossible to have detailed knowledge about all blocks and their interaction.We introduce a simulation-based automation technique to support design understanding. Based on use cases provided by the designer and on their coverage information, the proposed technique identifies parts of the source code that are relevant for a certain functional feature. In two case studies the technique is shown to be at least as exact as reading the documentation with two important advantages: the automated approach is faster and more precise than the existing documentation for the inspected designs.

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Section: Preliminariesmentioning

confidence: 99%

Automated feature localization for hardware designs using coverage metrics

Malburg

Finder

Fey

2012

Proceedings of the 49th Annual Design Automation Conference

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show abstract

“…For Verilog or VHDL several approaches and tools exists (for an overview see e.g. [16]). However, to the best of our knowledge no code coverage method to measure the quality of a SystemC testbench has been proposed.…”

Section: Related Workmentioning

confidence: 99%

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

Große

Peraza

Klingauf

et al. 2008

Embedded Systems Specification and Design Languages

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The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modeling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction levels can easily be built. But the fault coverage of a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology.

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“…An overview on the respective coverage metrics to qualify the testbenches can be found e.g. in [5]. However, these metrics cannot be used for coverage analysis in formal verification because formal methods traverse the underlying Finite State Machine (FSM) of the circuit exhaustively.…”

Section: Introductionmentioning

confidence: 99%

A guiding coverage metric for formal verification

Haedicke¹,

Grosse²,

Drechsler³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation.In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.

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Coverage metrics for functional validation of hardware designs

Cited by 180 publications

References 27 publications

Automated feature localization for hardware designs using coverage metrics

Automated feature localization for hardware designs using coverage metrics

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

A guiding coverage metric for formal verification

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