Critical Elements for Next Generation High Performance Computing Nanosheet Technology

Bao, R.; Durfee, C.; Zhang, J.; Qin, L.; Rozen, J.; Zhou, H.; Li, J.; Mukesh, Sagarika; Pancharatnam, S.; Zhao, K.; Adams, C. D.; Leobandung, E.; Narayanan, V.; Guo, D.; Bu, H.

doi:10.1109/iedm19574.2021.9720601

Cited by 12 publications

(6 citation statements)

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“…Then, a Si layer was epitaxially grown before the S/D epitaxial growth presented in Figure 2 c, the aim of which is to prevent damage to the SiGe S/D region of the PMOS when the sacrificial Si 0.5 Ge 0.5 layer is removed in the subsequent steps. STI in the channel width direction was performed to etch down a bit (see Figure 2 e) and a side of the SiGe layer was exposed to facilitate the subsequent sacrificial Si 0.5 Ge 0.5 layer etching, which is the most critical step in Full BDI_Last fabrication, as shown in Figure 2 f. Additionally, Si 0.7 Ge 0.3 was damaged a little (about 0.5–1 nm) according to the high selective etch ratio (at least 1:20) of Si 0.7 Ge 0.3 to Si 0.5 Ge 0.5 [ 27 ]. Figure 2 g shows that the dielectric is filled into the original sacrificial Si 0.5 Ge 0.5 layer to form the full BDI structure.…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

Yang,

Huang,

Wang

et al. 2023

Micromachines

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In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

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Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

Yang,

Huang,

Wang

et al. 2023

Micromachines

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“…After single gate patterning, a 20-nm-thick Al2O3 layer deposited through ALD was used to prevent Ge NW bending from subsequent etching process. The upper Ge was then implanted with 11 B ions (1E15 cm -2 dosage at 10 keV) for p-type Ge S/D regions. Following that, a 20-nm-thick SiO2 was deposited by PECVD.…”

Section: Device Fabricationmentioning

confidence: 99%

“…in field-effect transistor (FinFET) [1]- [3], gate-all-around (GAA) nanowire (NW) FET [4]- [8], and nanosheet (NS) FET [9]- [11] have been proposed for the continuous scaling down of CMOS with superior electrostatics and device performance. Currently, the structure of complementary FET (CFET) with stacked pFET and nFET can further reduce the layout area and meet the demand of performance beyond 3-nm node (N3) [12].…”

Section: Introductionmentioning

confidence: 99%

3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

Lin,

Chen

et al. 2023

IEEE J. Electron Devices Soc.

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In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of 166 A/m at VD = VG-VTH = -0.5 V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of 3.03 × 10 5 , 3.4 × 10 4 at VD = -0.05 V and -0.5 V, respectively. The Si nFinFET presents an ION of 60.4 A/m at VD = VG-VTH = 0.5 V and shows SSmin of 91, 101 mV/dec, and ION/IOFF of 9.01 × 10 4 , 5.62 × 10 5 at VD = 0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node.

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“…Vertically stacked GAA NS FET, also known as multi-bridge-channel FET [1][2][3][4] and GAA nano-ribbon FET [5], represents a significant leap forward from traditional planar and FinFET devices as it offers superior electrostatics, alleviates short channel effects, provides higher effective device width per footprint, and allows flexibility in power and performance tuning with variable sheet width enabled by single-exposure EUV lithography [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A Review of Reliability in Gate-All-Around Nanosheet Devices

Wang

2024

Micromachines

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The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling.

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Critical Elements for Next Generation High Performance Computing Nanosheet Technology

Cited by 12 publications

References 0 publications

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

A Review of Reliability in Gate-All-Around Nanosheet Devices

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