Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Abstract

Abstract-Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ∆Σ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

“…These results show an improvement in the maximum sampling frequency with a factor of 2 to 3 with respect to the non-TI CIFB DSM [3] and 8-channel TI MASH [4]. In comparison with the 2-channel TI MASH [5], the proposed architecture doesn't require the use of an additional DAC, allows bandwidth configurability and consumes ~ 6 times less.…”

“…The architectures in [4][5] use the popular block digital filtering method for time-interleaving, introduced over 20 years ago in [6]. This method is based on poly-phase components and results in an effective sampling frequency of Mf S , where M is the number of cross-coupled DSMs operating at the sampling frequency f S .…”

“…A solution is to introduce time-interleaved (TI) operation, thus relaxing the timing constraints of the system [4][5][6][7]. A 2 nd order multi-stage noise shaping (MASH) architecture with 8 TI channels is presented to work at an effective sampling frequency of 2.5 GHz while consuming 6.9 mW [4].…”

“…A 2 nd order multi-stage noise shaping (MASH) architecture with 8 TI channels is presented to work at an effective sampling frequency of 2.5 GHz while consuming 6.9 mW [4]. An extended study of the critical path for a similar architecture is performed in [5] in order to increase the sampling frequency up to 8 GHz, though the power consumption is 10 times larger than in [4]. Nevertheless, the MASH architecture has a multi-bit output which requires the use of an additional Digital-to-Analog Converter (DAC) and doesn't allow bandwidth configurability, since all the zeros of the noise shaping function are located at DC.…”