Critical-reliability path identification and delay analysis

Abstract

Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential reliability hazards in the postsilicon stage, current large-scale designs for commercial implementation overpessimistically analyze circuit aging under assumed worst-case workload in order not to violate the corner cases even for low possibilities, thus introducing unnecessary margin in the design timing analysis. The major issue is lack of an effective aging analysis method applicable to large designs with low CPU runtime, which is mainly due to: (1) conventional reliability tools are extremely timeconsuming for circuit-level timing analysis and thus are not practical for large designs; (2) mathematical models developed to expedite the process are not accurate due to the high complexity of aging effects. In this article, a comprehensive analysis is presented to highlight the importance of each aging parameter. Then, a novel methodology is developed based on current commercial reliability tools to guarantee its high accuracy on circuit-level aging analysis. Existing proven low-level mathematical models are further enhanced to extensively speed up a higher level analysis by taking advantage of the explicit intermediate conditions stored in a pregenerated lookup table. Our results indicate ≥244X improved computational efficiency, ≤5% relative error, and ≤0.7% absolute error compared with commercial reliability analysis tools (e.g., HSPICE MOSRA).

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

“…To simulate the effect of NBTI, an efficient simulation analysis and an accurate aging model are required to translate the amount of electrical stress into device parameter degradation. There are three major industry-standard aging simulators, namely, Hewlett simulation program with integrated circuit emphasis (HSPICE) MOSRA from Synopsys, RelXpert from Cadence, and Eldo from Mentor Graphics [16]. In this work, we used MOSRA to model the circuit degradation behavior in the experiment.…”

On improving dependability of analog and mixed-signal SoCs

“…The reliability issues and corresponding solutions during their operational life are never considered in the current practices. 7) The reliability analysis tools are usually very slow [Che14] and sometime it is very difficult to simulate larger and complex designs. Therefore, only small circuits are normally considered and analysed in these simulations [Jha05].…”