Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

Abstract

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new "fatal" via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the "fatal" via ratio.Keywords -time-dependent dielectric breakdown, low-k soft breakdown, Cu interconnect, low-k hard breakdown, reliability, Schottky emission, Poole-Frenkel, low-k TDDB voltage acceleration, low-k via TDDB, I-V conduction slope

Manufacturable nanometer designs using standard cells with regular layout

“…The vias in the interconnect stack have the highest reliability concerns [23], [24], [25], [26], [27] and incorporating regularity at the lower levels of abstraction shows clear benefits with the UR implementations using the lowest number of vias as is evident from Fig. 2b.…”

Reasonable circuit analysis considering comprehensively reliability and variability

“…One is the hard breakdown (HBD), which is not completely usable, and the other is the soft breakdown (SBD), which is when a gate current gradually increases before the HBD [4][5][6]. If in a state of SBD the characteristics such as delay are not influenced by degradation very much, it is not necessary to consider such conditions in real design.…”

“…The first is principally reliability factors by which device characteristics deteriorate with time, so-called time degradation, which include timedependent dielectric breakdown (TDDB) [4][5][6], negative bias temperature instability (NBTI) [1][2][3][7][8][9], hot-carrier injection (HCI) [1][2][3], electromigration (EM) [10][11][12][13][14], stress migration (SM), etc. The second is mainly design-dependent factors, which include latch up, electrostatic-discharge (ESD), electromagnetic interference (EMI), power-supply/crosstalk/substrate noises, and also soft-error as a design approach.…”

Scaled CMOS reliability and considerations for spacecraft systems: Bottom-up and top-down perspectives

“…Low-k dielectrics are used in more advanced processes, and metal from the contacts can migrate within the dielectric materials. This process is quite different from CMOS processes with larger feature sizes, which do not use the new insulator materials [7]. Recent information on via reliability from a 32 nm process shows that this reliability problem changes in character for highly scaled devices.…”

“…Figure 3. Metal-insulator transition in the low-k dielectric material used for interconnects in an advanced 32 nm process [7]. The leakage takes place between the materials used in multi-level metallization regions.…”