Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems

Coskun, Ayse K.; Eris, Furkan; Joshi, Ajay; Kahng, Andrew B.; Ma, Yenai; Narayan, Aditya; Srinivas, Vaishnav

doi:10.1109/tcad.2020.2970019

Cited by 27 publications

(3 citation statements)

References 30 publications

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“…The total power of the laser, SOA, DAC, and ADC in E-O-E control for 5 parallel read operations is 9.3mW , resulting in a read energy of 11.6pJ/bit for COSMOS-4bit. The energy consumed in the electrical links connecting the processor and the E-O-E control unit is < 1pJ/bit [22]. For EPCM, we use NVSim [25] to compute the energy-per-bit for read and write operations.…”

Section: A Cosmos Vs Epcmmentioning

confidence: 99%

Architecting Optically-Controlled Phase Change Memory

Narayan¹,

Thonnart²,

Vivet³

et al. 2021

Preprint

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Phase Change Memory (PCM) is an attractive candidate for main memory as it offers non-volatility and zero leakage power, while providing higher cell densities, longer data retention time, and higher capacity scaling compared to DRAM. In PCM, data is stored in the crystalline or amorphous state of the phase change material. The typical electrically-controlled PCM (EPCM), however, suffers from longer write latency and higher write energy compared to DRAM and limited multi-level cell (MLC) capacities. These challenges limit the performance of data-intensive applications running on computing systems with EPCMs.Recently, researchers demonstrated optically-controlled PCM (OPCM) cells, with support for 5 bits/cell in contrast to 2 bits/cell in EPCM. These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidthdensity silicon-photonic links. The higher MLC capacity in OPCM and the direct cell access using optical signals enable an increased read/write throughput and lower energy per access than EPCM. However, due to the direct cell access using optical signals, OPCM systems cannot be designed using conventional memory architecture. We need a complete redesign of the memory architecture that is tailored to the properties of OPCM technology.This paper presents the design of a unified network and main memory system called COSMOS that combines OPCM and silicon-photonic links to achieve high memory throughput. COSMOS is composed of a hierarchical multi-banked OPCM array with novel read and write access protocols. COSMOS uses an Electrical-Optical-Electrical (E-O-E) control unit to map standard DRAM read/write commands (sent in electrical domain) from the memory controller on to optical signals that access the OPCM cells. Our evaluation of a 2.5D-integrated system containing a processor and COSMOS demonstrates 2.14× average speedup across graph and HPC workloads compared to an EPCM system. COSMOS consumes 3.8× lower read energy-per-bit and 5.97× lower write energy-per-bit compared to EPCM. COSMOS is the first non-volatile memory that provides comparable performance and energy consumption as DDR4 in addition to increased bit density, higher area efficiency and improved scalability.

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Section: A Cosmos Vs Epcmmentioning

confidence: 99%

Architecting Optically-Controlled Phase Change Memory

Narayan¹,

Thonnart²,

Vivet³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

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“…As Moore's Law scaling is nearing its end, the traditional monolithic silicon chip, for which a flaw in one part can make the entire device unusable, is being abandoned in favor of systemson-chip (SoC), composed of multiple small chiplets leading to less complex integrated circuits, which can be built in the most efficient manufacturing process according to their characteristics. Advanced packaging technologies and substrate design, which allows for much higher bandwidth between chiplets, have enabled integrating chiplets from different manufacturing process flows into a single package [2,11,22,26]. Thus, disintegrating complex chips improves yield and reduces costs, while accommodating more easily specialized systems, with the net result of being nowadays adopted by most major hardware manufacturers in their current micropro-nario, these fundamental libraries will suffer from the rapid evolution on the complexity of architectures, and hence techniques and methodologies for rapid adaptation will become mandatory.…”

Section: Introductionmentioning

confidence: 99%

Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures

Catalán

Igual

Herrero

et al. 2023

Journal of Parallel and Distributed Computing

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“…PCBs are mature and cost-effective, but their lengthy and wide traces cause a high inductance and capacitance, restricted bandwidth and substantial power losses [2,3]. As a result, interposer-based 2.5-D IC integration has received a lot of interest as a way to overcome the constraints of 2-D IC integrations [4,5]. Based on an interposer, 2.5-D IC integration separates a single SoC into numerous functional blocks known as chiplets, which are placed side-by-side on the interposer and coupled with high speed and bandwidth through the interposer.…”

Section: Introductionmentioning

confidence: 99%

New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

et al. 2022

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A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

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Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems

Cited by 27 publications

References 30 publications

Architecting Optically-Controlled Phase Change Memory

Architecting Optically-Controlled Phase Change Memory

Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures

New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

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