Crosstalk noise analysis of on-chip interconnects for ternary logic applications using FDTD

Madhuri, Badugu Divya; Sunithamani, S.

doi:10.1016/j.mejo.2019.104633

Cited by 21 publications

(12 citation statements)

References 25 publications

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“…However, this effect is quite small; thus the performance parameters are almost unaffected by a slight change in the channel length. The stability analysis for different CNT diameters and the channel length is carried out by considering the electrical equivalent circuit model of CNTFET presented in (Deng and Wong, 2007; Madhuri and Sunithamani, 2019). This model is a physics-based model that includes nonidealities such as quantum confinement effects in both circumferential and longitudinal directions of the channel.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

Design of ternary subtractor using multiplexers

Kolanti¹,

Patel²

2021

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Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Design of ternary subtractor using multiplexers

Kolanti¹,

Patel²

2021

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“…The proposed model is validated by comparison it to conventional FDTD model and with HSPICE simulation. The interconnects load is driven by CMOS driver, the interconnects dimensions are taken from ITRS [27,28]. At 22nm technology node, the interconnect is placed from a ground plane is 99nm.…”

Section: The Mrtd Model Is Compared and Validationmentioning

confidence: 99%

Crosstalk Noise Analysis in Coupled On-Chip Interconnects Using MRTD Technique

Gugulothu

2021

Preprint

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In this paper, the Crosstalk noise analysis of coupled on-chip interconnects have been analyzed. The multiresolution time-domain method (MRTD) is used to analyze the crosstalk noise model. The crosstalk induced propagation time delay and crosstalk peak voltage on the victim line of interconnects have been determined and compared to those of the conventional finite difference time domain (FDTD) method and validated with HSPICE simulations at the 22nm technology node. The results of the proposed method shows that crosstalk induced propagation delay in dynamic in-phase, out-phase and peak voltage timing, as well as the peak voltage value for functional crosstalk in the copper interconnects are an average error of less than 0.53% for the proposed model and HSPICE simulations. The results of the proposed model are closely similar to those of HSPICE simulations. Electromagnetic interference and electromagnetic compatibility of on-chip interconnects can also be addressed using the proposed method.

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“…The connection between first stage and second stage improves inspeed and area, though it has significant power consumptionThe direct connections from first stage to second stage output nodes, endure a large voltage swing which results in kick-back noise [5] [6]. To perform comparison in two-stage comparators, we require both clock and inverted signal.…”

Section: Related Workmentioning

confidence: 99%

Cross Coupled Differential High Speed Comparator

Rooban,

Sri,

Jayaram

et al. 2019

IJEAT

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Power efficiency and high speed comparator is presented. ,n-MOS transistors are used to design preamplifier stage and the latch stage. Both stages are controlled by a special clock circuit. By using clock circuit we can achieve enough preamplification gain. At the evaluation phase, the latch is activated with a delay to obtain sufficient pre-amplification gain and avoid extra power consumption. At this phase transistors are cross coupled to increase the preamplifier gain and to lower the input voltage common mode of the latch is used to strongly activate the n-MOS transistors (on the latch input) and reduce the delay. This circuit is designed with n-MOS transistors due to its inherent superiority over the p-MOS transistor. The proposed cross coupled comparator reduces the power and delay compared to conventional CMOS comparators.

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Crosstalk noise analysis of on-chip interconnects for ternary logic applications using FDTD

Cited by 21 publications

References 25 publications

Design of ternary subtractor using multiplexers

Design of ternary subtractor using multiplexers

Crosstalk Noise Analysis in Coupled On-Chip Interconnects Using MRTD Technique

Cross Coupled Differential High Speed Comparator

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