This paper presents the finite-difference time-domain model of nonuniform interconnects including skin effect losses based on the current mode signaling (CMS). For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects. These effects are incorporated in the proposed model using the modified alpha power law model. Additionally, high-frequency losses are incorporated in the proposed model that further improves the accuracy. Using the proposed model, the performance of nonuniform interconnects is investigated using the CMS scheme. Timedomain analysis model is derived from CMS nonuniform interconnects using finite-difference time-domain technique. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The efficiency of CMS interconnects is evaluated by comparing with conventional voltage mode signaling interconnects. The propagation delays and dynamic and functional cross talk effects at the far end of the coupled nonuniform interconnect are analyzed at the 32-nm technology node. The proposed model results are validated using the standard HSPICE simulations. KEYWORDS CMS, cross talk and propagation delay, FDTD, nonuniform interconnects, skin effects | INTRODUCTIONThe sustained technology scaling in very-large-scale integration leads to high complexity in integrated circuits. Due to scaling of technology, interconnect delays are more dominant than the gate delays. Billions of transistors are fabricated in a single chip causing high density and reduction in dimensions of the on-chip components. 1 As the global interconnects have increased lengths, delay due to parasitic components like resistor (R), capacitor (C), inductance (L), and conductance (G) are more that dominates other scaled device delays. The major source of delay and power dissipation is interconnects in miniaturized devices. These interconnects are not always uniform; they are mostly nonuniform in nature due to their complexity and particular design specifications at corners and edges of interconnect.The demand for the high-speed devices increases with the scaling of the technology; as a result, the frequency dispersion losses and noise takes place with high operating frequencies. 2,3 Due to the intersymbol interference problem in the received signal, the bit error rate increases eventually. Equalization techniques are used to diminish this nonideal effect. Different procedures, to be specific decision feedback equalization, linear equalization, pre-emphasis, deemphasis, and adaptive equalization, have been accounted for equalization techniques in interconnects. 4 The noise in

This paper presents an accurate structure for multilayer graphene nanoribbon (MLGNR) bundled interconnects to reduce the effects of crosstalk in ternary logic circuits. In the proposed structures, the signal line is surrounded by the shielding lines to reduce the crosstalk effects. The crosstalk effects such as noise peak, noise area, delay, and power consumptions are compared to effects produced by conventional methods. The impacts of process variation in the proposed structures are also presented. Additionally, the proposed MLGNR interconnect results are compared with the carbon nanotube interconnections. All the proposed circuits are implemented and simulated using HSPICE tool. The simulation results indicated that the passively shielded MLGNR interconnects provide lower crosstalk effects up to 47.7% and 69.4%, respectively, over the active and without shielded interconnects. K E Y W O R D S active and passive shieldings, crosstalk, multilayer graphene nanoribbon, ternary logic 1 | INTRODUCTION Traditionally, copper is promising interconnect material used in very large scale integrated (VLSI) circuits. Due to shrinking the VLSI technology into nanometer, it is needed to scale the dimensions of Cu on-chip interconnects. Scaling the Cu dimensions has created the surface and grain boundary scatterings that increases the interconnect resistance and capacitance. Additionally, the effects such as electromigration, skin effect, small mean free path (MFP), less electrical and thermal conductivity, stress, and process variability issues affect the Cu interconnect performance. Thus, researchers found alternative technologies such as carbon nanotubes (CNTs) 1,2 and graphene nanoribbons (GNRs). 3,4 With the invention by Iijima, 5 researchers are attracted to CNTs because of their superior properties such as capability of carrying large currents, large thermal conductivity, and mechanical strength. 6 The shape of the CNTs can be roll of hollow graphene sheets in tube shape, thus it is referred as CNTs. The CNTs act either as semiconductor or conductor depending on the rolling angle, i.e., chirality. Based on the physical properties, CNTs can be categorized as singlewalled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs). As the name depicts, the SWCNT is a single rolled sheet of graphene has radius ranges from 0.2 to 2 nm, while the MWCNT contains multiple concentric SWCNTs. The SWCNTs can be utilized as channel in field-effect transistors (FETs) as well as the metal in on-chip interconnects. 7 But the MWCNT suits only for implementing the interconnects because of its larger diameter. Meanwhile, in on-chip interconnects, MWCNTs provide better performance over the SWCNTs as they have more conducting shells, large MFP, low resistance, and large ballistic transport. 8,9

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

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