Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

This paper presents the finite-difference time-domain model of nonuniform interconnects including skin effect losses based on the current mode signaling (CMS). For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects. These effects are incorporated in the proposed model using the modified alpha power law model. Additionally, high-frequency losses are incorporated in the proposed model that further improves the accuracy. Using the proposed model, the performance of nonuniform interconnects is investigated using the CMS scheme. Timedomain analysis model is derived from CMS nonuniform interconnects using finite-difference time-domain technique. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The efficiency of CMS interconnects is evaluated by comparing with conventional voltage mode signaling interconnects. The propagation delays and dynamic and functional cross talk effects at the far end of the coupled nonuniform interconnect are analyzed at the 32-nm technology node. The proposed model results are validated using the standard HSPICE simulations. KEYWORDS CMS, cross talk and propagation delay, FDTD, nonuniform interconnects, skin effects | INTRODUCTIONThe sustained technology scaling in very-large-scale integration leads to high complexity in integrated circuits. Due to scaling of technology, interconnect delays are more dominant than the gate delays. Billions of transistors are fabricated in a single chip causing high density and reduction in dimensions of the on-chip components. 1 As the global interconnects have increased lengths, delay due to parasitic components like resistor (R), capacitor (C), inductance (L), and conductance (G) are more that dominates other scaled device delays. The major source of delay and power dissipation is interconnects in miniaturized devices. These interconnects are not always uniform; they are mostly nonuniform in nature due to their complexity and particular design specifications at corners and edges of interconnect.The demand for the high-speed devices increases with the scaling of the technology; as a result, the frequency dispersion losses and noise takes place with high operating frequencies. 2,3 Due to the intersymbol interference problem in the received signal, the bit error rate increases eventually. Equalization techniques are used to diminish this nonideal effect. Different procedures, to be specific decision feedback equalization, linear equalization, pre-emphasis, deemphasis, and adaptive equalization, have been accounted for equalization techniques in interconnects. 4 The noise in

Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs). Design/methodology/approach To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism. Findings The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET. Originality/value This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

The simultaneous switching noise (SSN) effects in graphene nanoribbon field effect transistor (GNRFET) based ternary circuits are presented in this study. The performance in terms of SSN induced peak noise and propagation delay on power and ground rails are investigated in multilayer graphene nanoribbon (MLGNR) bundled power interconnects using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulator. Furthermore, these investigations are compared to the copper (Cu) and multiwalled carbon nanotubes (MWCNT) based power interconnects. From the results, it is noticed that the proposed MLGNR interconnects shows performance improvements up to 74.9% and 33.8% over the Cu and MWCNT interconnects. Moreover, the SSN peak noise and delay are investigated for different interconnect lengths from 200 to 500 μm. It is observed that the SSN noise on power and ground rail is reduced and propagation delay is increased as interconnect length is increased.