This paper presents a unique method to reduce the crosstalk noise, power consumption, power delay product (PDP) and energy delay product (EDP) in coupled multi-walled carbon nanotube (MWCNT) based through silicon vias (TSVs) with polymer liners. A novel structure of TSVs is proposed, where the MWCNT bundles are placed as conducting material and polymer liners are placed as dielectric material. The electrical equivalent model of the proposed TSVs is used and simulated in HSPICE to evaluate the performance. The performance analysis determines that there is a significant improvement in crosstalk noise, power consumption, PDP and EDP for polymer liners such as polyimide, polypropylene carbonate (PPC) and benzocyclobutene (BCB) over the conventional silicon dioxide (SiO 2 ) liner. Moreover, the performance is also analyzed by varying the pitch between the TSVs from 100 μm to 3000 μm. It is noted that the induced crosstalk noise issues are reduced as the TSV pitch is increased. Similarly, the power consumption, PDP and EDP of the proposed TSVs are also reduced for the high pitch value. From the simulation results, it is observed that the proposed MWCNT TSVs with BCB liner show improvements up to 18.01%, 35.37% and 49.06%, respectively in terms of power consumption, PDP and EDP over the TSVs with SiO 2 liner.

Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

The investigation of crosstalk issues for coupled through silicon vias (TSVs) in ternary logic is presented in this study. The crosstalk issues are analyzed for coupled TSVs utilizing multi-walled carbon nanotube (MWCNT) as conductive filler, and polymer liners such as polyimide, polypropylene carbonate, and benzocyclobutene (BCB) as insulating materials. For the coupled TSVs, the electrical equivalent circuit model is used to investigate the crosstalk which is driven by the ternary inverter. Based on the Hewlett simulation program with integrated circuit emphasis simulations, the effects of crosstalk such as functional and dynamic crosstalk for proposed TSVs are compared with single-walled CNT (SWCNT) TSVs. Furthermore, the other performance parameters such as power dissipation, power delay product (PDP), and energy delay product are investigated. The crosstalk effects of the proposed model are also examined for various TSV heights. It is noticed that the BCB based coupled MWCNT TSVs provide a significant improvement in crosstalk at reduced TSV height. It is also noticed that the proposed TSVs improved the overall performance up to 30.21% compared to the SWCNT based TSVs. Hence, the MWCNT based TSVs with BCB liner are most suitable for ternary logic integrated circuits over the conventional TSVs.

Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs). Design/methodology/approach To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism. Findings The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET. Originality/value This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

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