Crosstalk Noise of Octagonal TSV Array Arrangement Based on Different Input Signal

Abstract

This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure.

Application and Prospect of Artificial Intelligence Methods in Signal Integrity Prediction and Optimization of Microsystems

“…With the development requirements of 5G, Internet of Things (IoT), and artificial intelligence (AI) for intelligent and high-performance electronic systems, electronic systems are developing towards high performance, miniaturization, and intelligence, and have been widely used in high-performance computing, smart medical care, autonomous driving, IoT, smart wear and additional devices [ 1 , 2 , 3 , 4 , 5 ]. However, as the miniaturization of feature size gradually approaches the atomic limit, the principle of improving chip performance along Mole’s law gradually fails [ 6 , 7 , 8 ]. Microsystem technology based on advanced packaging is the latest effective means to promote the development of electronic systems to superior performance and miniaturization [ 9 , 10 , 11 ].…”

Special Issue “Building Three-Dimensional Integrated Circuits and Microsystems”

“…The selection of a crucial parameter for achieving the TSV process is linked to the selection of process technology, which ultimately dictates the TSV performance to a significant degree. The proposed scheme achieves an obvious improvement in reducing system noise and area and provides a learning idea for future related research [6].…”