Crosstalk reduction for VLSI

Vittal, Ashok; Marek-Sadowska, Malgorzata

doi:10.1109/43.594834

Cited by 242 publications

(126 citation statements)

References 18 publications

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“…The observed peak reductions in (worst-case delay, delay uncertainty) for various technology nodes are as follows. 5 • 130nm: (31.5%, 33.7%)…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…We have given good, general swizzling pattern constructions, and empirically computed the optimal number of swizzles for typical global buffered 4 Worst-case delay is not monotonically decreasing with number of swizzles as the impact of extra wires and vias starts to dominate after a certain optimal number of swizzles. 5 The reader may point out that this intentional shift in arrival times may be offset to some extent by process variations. However, since swizzling is done on neighboring lines, there would tend to be a strong spatial correlation of variation such that process variations will not tend to impact the relative delays of the swizzled lines.…”

Section: Discussionmentioning

confidence: 99%

“…They swap segments of different nets but since they do not split the horizontal or vertical segments of the initial route, their approach is essentially the same as the track assignment approach followed in [6]. Vittal et al [5] present a new crosstalk model which is not as pessimistic as the charge-sharing model; they determine whether a given routing solution will fail due to coupling noise but ignore the issue of coupling delay. Kirkpatrick et al [6] propose a track assignment algorithm to minimize channel width while obeying crosstalk constraints on all the nets.…”

Section: Related Workmentioning

confidence: 99%

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Manufacturing-aware physical design

Gupta¹,

Kahng²

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution -swizzling -which reduces worst-case coupling delay for long parallel wires such as in wide on-chip global buses. We understand that swizzling is a folklore in structured-custom design community but we are the first to describe the method and analyze the potential benefits in literature. We give a general method for construction of good swizzling patterns. We also give empirically determined, optimal swizzling patterns for various technology nodes and typical repeater intervals. From our results, we see up to 31.5% reduction in worst-case delay and 34% reduction in delay uncertainty.

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“…The observed peak reductions in (worst-case delay, delay uncertainty) for various technology nodes are as follows. 5 • 130nm: (31.5%, 33.7%)…”

Section: Experiments and Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Manufacturing-aware physical design

Gupta¹,

Kahng²

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…[7] derives bounds for crosstalk noise using a lumped model but assuming a step input for aggressor driver. The peak noise expression in [7] is extended by [8], [9] to consider a saturated ramp input and a π circuit to represent the interconnect. These models fail to represent the distributed nature of the interconnect.…”

Section: Introductionmentioning

confidence: 99%

“…Then capacitance values are set to be C 1 = C s /2, C 2 = (C s + C e )/2 and C L = C e /2 + C1. Compared with [12], [13]which only used one lumped RC for the victim net, it is obvious that our 2-π model can model the coarse distributed RC characteristics. In addition, since we consider only those key parameters, the resulting 2-π model can be solved analytically.…”

mentioning

confidence: 99%

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Hunagund¹,

Kalpana²

2011

IJET

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Abstract-Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.Index Terms-Aggressor, Coupling, Crosstalk, Interconnect noise, Wire spacing, I. INTRODUCTIONAdvancement in the field of very large scale integration (VLSI) have lead to a decrease in device geometries (deep submicron technology), high device densities, high clock rates, and thus small signal transition times. Thus, interconnection lines that were once considered to be electrically isolated can now interfere with each other and have an important impact on system performance and correctness. One such interaction caused by parasitic coupling between wires is known as crosstalk. If not carefully considered during design validation, crosstalk can cause extra signal delay, logic hazards, and even circuit malfunction. Accurate modeling and simulation of interconnect delay due to crosstalk thus becomes increasingly important in the design of high-performance integrated circuits.The net on which noise is being induced is called the victim net whereas the net that induces this noise is called the aggressor net. Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages. Any such tool requires fast yet accurate crosstalk noise models both to estimate noise and also to see the effects of Manuscript received September 19, 2011; revised December 3, 2011. P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India (e-mail:prabhakar.hunagund@gmail.com).A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India (e-mail: abkalpana@gmail.com).various interconnect and driver parameters on noise. Several papers, which propose crosstalk models, can be found in recent literature. In [6], telegraph equations are solved directly to find a set of analytical formulae for peak noise in capacitively coupled bus lines. [7] derives bounds for crosstalk noise using a lumpe...

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A bus delay reduction technique considering crosstalk

Hirose

Yasuura

2001

Electron Comm Jpn Pt III

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Recently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay a serious problem in deep micron LSI design. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. This paper proposes an on‐chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the approximate bus delay, delay reduction can be achieved by applying the proposed technique to repeater‐inserted on‐chip buses. The result of SPICE simulation also shows that at most a 20% reduction of the total bus delay can be achieved. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 85(1): 24–31, 2002

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Crosstalk reduction for VLSI

Cited by 242 publications

References 18 publications

Manufacturing-aware physical design

Manufacturing-aware physical design

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

A bus delay reduction technique considering crosstalk

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