Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

IEEE Electron Device Lett.

Enz

2020

Self Cite

162

Measurements in field-effect transistors have indicated that the Boltzmann thermal limit of the subthreshold swing, (k B T /q) ln 10, is not followed down to deep-cryogenic temperatures. Instead, there is a nonlinear deviation from this limit which cannot be explained with the present theory. In this paper, we derive a new theory which resolves this discrepancy by including the source-drain tunneling through a band tail. We demonstrate that the additional tunneling component of the current becomes dominant over the diffusion current at a sufficiently low cryogenic temperature. A band tail in the electrostatics, with only diffusion transport, does not explain the excess subthreshold swing at deep-cryogenic temperatures, neither does only self-heating, nor does a nonuniform density of interface traps in the bandgap with Fermi-Dirac occupation. The proposed theory is experimentally validated with our measurements in advanced CMOS technology down to 4.2 K. Finally, we assess the obtained densities of interface traps in the presence of band-tail tunneling.

Section: Solving the Singularity Related To Interface Statescontrasting

confidence: 78%

Section: Introductionmentioning

confidence: 99%

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

IEEE Electron Device Lett.

Enz

2020

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162

“…5-c). Note that the largest V th -increase is observed for pMOS, similarly to a 28-nm bulk process [29]. Furthermore, the maximum G m,sat and G m,lin (Figs.5d-e) improve down to 4.2 K, e.g.…”

Section: Subthreshold Swing Threshold Voltage Transconductance Andmentioning

confidence: 82%

“…From this method, it can be expected that the low-doped thin film of silicon in a FDSOI MOSFET can be completely ionized at cryogenic temperature depending on the relative bias points of the front and back gates. In this work, as an initial investigation prior to further physical and compact modeling, we perform a cryogenic characterization and semi-empirical modeling of a commercial ultra-thin-body 28-nm FDSOI CMOS technology at temperatures down to 4.2 K, similar to earlier work on a commercial 28-nm bulk CMOS technology [29]. The low-temperature dc measurements (transfer and output characteristics) and the characterization down to 4.2 K are presented in Sec.…”

mentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Solid-State Electronics

Bohuslavskyi

et al. 2019

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physicsbased cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.The birth of CMOS-compatible qubits in silicon [1,2,3,4] has rebooted the interest in cryogenic CMOS electronics for computing applications. Since the 1970s, MOSFET devices have been under investigation at cryogenic temperatures for use in custom applications, such as low-noise scientific equipment, spacecraft, power conversion etc. [5,6,7,8,9]. However, despite its many benefits for reaching high-performance and low-power computing [10], cryogenic cooling did not stay into practice for computing, abandoning the trend set by the ETA-10 liquid-nitrogen-cooled supercomputer [11].Nowadays, co-integrating qubits and CMOS circuits on the same substrate can greatly aid the development of scalable quantum computers featuring massive parallelism and error correction [12,13,14]. In this context, a silicon-on-insulator (SOI) platform is particularly attractive since the back gate provides additional control over the electron-spin qubit, trapped under the front gate of a SOI (nanowire) MOSFET[12,15,16]. To integrate the control circuits with quantum devices working at deep-cryogenic temperatures, regular SOI MOSFETs need to demonstrate reliable digital, analog and RF functionalities at such low temperatures. Using SOI cryogenic control electronics, the back gate can prove a useful tool to control the threshold voltage and hence the power consumption in circuits integrated close to the qubits [17], benefiting qubit coherence time by lowering generated noise. The main focus is on advanced ultra-thin body fully-depleted SOI (FDSOI) technology, e.g., the 28-nm node, to enable ultimate scalability of the resulting hybrid quantum-classical system [16,18].The 28-nm node, presently considered the ideal node for analog and RF applications at room temperature [19], has recently been tested for digital and analog functionality down to liquid-helium temperature (4.2 K) [17], and millikelvin temperature (20 mK) [20]. The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device c...

“…2c). Note that the largest V thincrease is observed for pMOS, similarly to a 28-nm bulk process [14]. Furthermore, the maximum G m,sat and G m,lin (Figs.2d-e) improve down to 4.2 K, e.g.…”

Section: Measurements and Characterizationmentioning

confidence: 81%

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Bohuslavskyi

et al. 2018

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In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.