This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems.

This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of the passive components, the pad parasitics were de-embedded from the test structures using an open fixture. The variations in capacitance, inductance and quality factor are explained in relation to the temperature dependence of the physical parameters, and the resulting insights on the modeling of passives at cryogenic temperatures are provided. Modeling the characteristics of on-chip passive components, presented for the first time down to 4.2 K, is essential in designing cryogenic CMOS radio-frequency integrated circuits, a promising candidate to build the electronic interface for scalable quantum computers.

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In this letter, we characterize the electrical properties of commercial bulk 40-nm MOSFETs at room and deep cryogenic temperatures, with a focus on quantum information processing (QIP) applications. At 50 mK, the devices operate as classical FETs or quantum dot devices when either a high or low drain bias is applied, respectively. The operation in classical regime shows improved transconductance and subthreshold slope with respect to 300 K. In the quantum regime, all measured devices show Coulomb blockade. This is explained by the formation of quantum dots in the channel, for which a model is proposed. The variability in parameters, important for quantum computing scaling, is also quantified. Our results show that bulk 40-nm node MOSFETs can be readily used for the co-integration of cryo-CMOS classical-quantum circuits at deep cryogenic temperatures and that the variability approaches the uniformity requirements to enable shared control.

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