2021
DOI: 10.1038/s41928-021-00687-6
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A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

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Cited by 64 publications
(29 citation statements)
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“…Fabricating the qubits and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds in error-correction protocols, and offer potential solutions to wiring and layout challenges [7,[77][78][79][80][81]. Integrating classical and quantum devices monolithically, using CMOS processes, enables the quantum processor to profit from the most mature industrial technology for the fabrication of large-scale circuits [35]. We show that this architecture allows for compilation strategies which inherit the favourable square-root scaling of compilation overhead in 2d structure and outperform the best in class compilation strategy of 1d chains, not only asymptotically, but also down to the minimal structure of a single square.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…Fabricating the qubits and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds in error-correction protocols, and offer potential solutions to wiring and layout challenges [7,[77][78][79][80][81]. Integrating classical and quantum devices monolithically, using CMOS processes, enables the quantum processor to profit from the most mature industrial technology for the fabrication of large-scale circuits [35]. We show that this architecture allows for compilation strategies which inherit the favourable square-root scaling of compilation overhead in 2d structure and outperform the best in class compilation strategy of 1d chains, not only asymptotically, but also down to the minimal structure of a single square.…”
Section: Discussionmentioning
confidence: 99%
“…We then investigate compilation strategies for the proposed 2d architecture and demonstrate a square-root scaling of the compilation overhead, which outperforms the linear overhead of 1d devices, not only asymptotically, but also down to its smallest building block which is likely to be investigated first in future experiments. This allows for balancing the trade-off between compilation overhead and creating space in between the qubit modules which can be beneficial for colocation of classical control and readout electronics [10,34,35] and alleviating contact routing issues [9,24,36,37]. Overall, this proposal should provide a compelling path to scaling, which could be manufactured with industrial CMOS processes.…”
Section: Introductionmentioning
confidence: 99%
“…1a has enabled important demonstrations over the past 20 years, it will become very cumbersome for few hundred qubits and may even be unachievable for the million of physical qubits that are required for fault tolerant quantum computing [10]. To avoid this wiring bottleneck, integrated cryogenic control platforms are being developed to control a larger number of spin qubits [9][10][11][12][13][14], while limiting the control electronics required at room temperature (See Fig. 1b).…”
Section: Introductionmentioning
confidence: 99%
“…1a and b) using DC signals, typically in the ±1 V range with at least a 100 µV resolution, while maintaining a thermal budget in the order of a milliwatt or below per DC source [9,11]. A first integrated solution based on switched-capacitor circuits and charge-locking, which is conceptually close to dynamic random access memories (DRAMs), has been proposed to perform simultaneous charge carrier confinement for several quantum dots [12,15]. However, this approach requires qubits that have similar electrical behaviour, which has yet to be demonstrated for silicon spin qubits.…”
Section: Introductionmentioning
confidence: 99%
“…This approach is also cheaper to implement experimentally as the qubit can be operated at temperatures up to 1 K and beyond while maintaining state initialization fidelities over 99.9%. Current efforts in scaling up spin qubit architectures [28][29][30] require on-chip control electronics that generate heat. Hence, initialization of spin qubits at higher temperatures [31][32][33][34][35][36], socalled hot qubits, is currently of very high interest.…”
Section: Introductionmentioning
confidence: 99%