Fabien Alibart received a Ph.D. in material science from University of Picardie Jules Verne, France, in 2008. He joined IEMN-CNRS in 2012 as a permanent researcher where he worked on the concepts of neuromorphic/bioinspired computing with emerging memory technologies. He is now with LN2-3IT CNRS as a researcher participating in the join laboratory program between France and Quebec (UMI-CNRS) where he is developing neuromorphic hardware for a variety of applications, from edge computing to brain-machine interfaces.

No abstract

Resistive switching and transport mechanisms of Al2O3/TiO2−x memristor crosspoint devices have been investigated at cryogenic temperatures down to 1.5 K, for the future development of memristor-based cryogenic electronics. We report successful resistive switching of our devices in the temperature range of 300–1.5 K. The current–voltage curves exhibit negative differential resistance effects between 130 K and 1.5 K, attributed to a metal–insulator transition of the Ti4O7 conductive filament. The resulting highly nonlinear behavior is associated with an ION/IOFF diode ratio of 84 at 1.5 K, paving the way for selector-free cryogenic passive crossbars. Temperature-dependent thermal activation energies related to the conductance at low bias (20 mV) are extracted for memristors in a low resistance state, suggesting hopping-type conduction mechanisms. Finally, the transport mechanism analysis at 1.5 K indicates that for all resistance states, the conduction follows the space-charge limited current model in low fields, whereas trap-assisted tunneling dominates in higher fields.

This study proposes voltage-dependent-synaptic plasticity (VDSP), a novel brain-inspired unsupervised local learning rule for the online implementation of Hebb’s plasticity mechanism on neuromorphic hardware. The proposed VDSP learning rule updates the synaptic conductance on the spike of the postsynaptic neuron only, which reduces by a factor of two the number of updates with respect to standard spike timing dependent plasticity (STDP). This update is dependent on the membrane potential of the presynaptic neuron, which is readily available as part of neuron implementation and hence does not require additional memory for storage. Moreover, the update is also regularized on synaptic weight and prevents explosion or vanishing of weights on repeated stimulation. Rigorous mathematical analysis is performed to draw an equivalence between VDSP and STDP. To validate the system-level performance of VDSP, we train a single-layer spiking neural network (SNN) for the recognition of handwritten digits. We report 85.01 ± 0.76% (Mean ± SD) accuracy for a network of 100 output neurons on the MNIST dataset. The performance improves when scaling the network size (89.93 ± 0.41% for 400 output neurons, 90.56 ± 0.27 for 500 neurons), which validates the applicability of the proposed learning rule for spatial pattern recognition tasks. Future work will consider more complicated tasks. Interestingly, the learning rule better adapts than STDP to the frequency of input signal and does not require hand-tuning of hyperparameters.

A key challenge in scaling quantum computers is the calibration and control of multiple qubits. In solid-state quantum dots (QDs), the gate voltages required to stabilize quantized charges are unique for each individual qubit, resulting in a high-dimensional control parameter space that must be tuned automatically. Machine learning techniques are capable of processing high-dimensional data—provided that an appropriate training set is available—and have been successfully used for autotuning in the past. In this paper, we develop extremely small feed-forward neural networks that can be used to detect charge-state transitions in QD stability diagrams. We demonstrate that these neural networks can be trained on synthetic data produced by computer simulations, and robustly transferred to the task of tuning an experimental device into a desired charge state. The neural networks required for this task are sufficiently small as to enable an implementation in existing memristor crossbar arrays in the near future. This opens up the possibility of miniaturizing powerful control elements on low-power hardware, a significant step towards on-chip autotuning in future QD computers.