This study investigated a novel forward body bias (FBB) analysis to optimize the threshold voltage (Vth) at cryogenic temperatures in the latest dynamic random-access memory (DRAM). Electrical measurements were conducted to analyze the cryogenic body bias effect in terms of performance, reliability, and short-channel effect in two types of transistors: DRAM peripheral low Vth transistors (Peri LVT) and buried-channel-array transistors (BCAT). At 77 K, the Vth shift (ΔVth) in BCAT was larger than that in Peri LVT due to the difference in channel doping concentration. It was observed that only BCAT experienced a decrease in saturation drain current (Id.sat) at cryogenic temperature because of the large ΔVth. To compensate for the ΔVth, FBB was applied to transistors. As a result, FBB effectively controlled the Vth and improved carrier mobility. Furthermore, this study demonstrated that FBB reduced hot-carrier degradation (HCD) at cryogenic temperature and improved short-channel effect, such as drain-induced barrier lowering (DIBL). These findings offer valuable solutions for optimizing cryogenic memory operation in quantum computing applications.INDEX TERMS Buried-channel-array transistor (BCAT), cryogenic, drain-induced barrier lowering (DIBL), forward body bias, hot-carrier degradation, threshold voltage.