Cryogenic ultra low power CMOS

Burr, James

doi:10.1109/lpe.1995.482473

Cited by 27 publications

(13 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1 when V in ¼ V out ) [6]. Figure 5(a) shows the measured voltage transfer characteristic (VTC) of an inverter at 65 mV with various well biases and confirms that sub-V th logic functions at room temperature below the previously reported low value of 70 mV [8]. In Figure 5(b), a butterfly curve for a 6T-SRAM cell is shown at a supply voltage of 70 mV, proving that sequential elements also maintain functionality well into the sub-V th regime.…”

Section: Circuit Characteristics At Ultralow-voltage Operationsupporting

confidence: 72%

Ultralow-voltage, minimum-energy CMOS

et al. 2006

View full text Add to dashboard Cite

Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in the subthreshold (V dd , V th ) regime, and suggest new strategies for energy-efficient design. We begin with a study at the device level, and we show that extreme sensitivity to the supply and threshold voltages complicates subthreshold design. The effects of this sensitivity can be minimized through simple device modifications and new device geometries. At the circuit level, we review the energy characteristics of subthreshold logic and SRAM circuits, and demonstrate that energy efficiency relies on the balance between dynamic and leakage energies, with process variability playing a key role in both energy efficiency and robustness. We continue the study of energy-efficient design by broadening our scope to the architectural level. We discuss the energy benefits of techniques such as multiple-threshold CMOS (MTCMOS) and adaptive body biasing (ABB), and we also consider the performance benefits of multiprocessor design at ultralow supply voltages.

show abstract

Section: Circuit Characteristics At Ultralow-voltage Operationsupporting

confidence: 72%

Ultralow-voltage, minimum-energy CMOS

et al. 2006

View full text Add to dashboard Cite

show abstract

“…Based on Equations 1 and 2, relative noise margins improve at low voltage because V t / V dd increases [16]. As discussed in [16], internal noise scales at least as fast as the supply voltage.…”

Section: Noise Marginsmentioning

confidence: 97%

“…As discussed in [16], internal noise scales at least as fast as the supply voltage. For long channel devices, capacitive coupling noise scales as V dd , resistive coupling noise scales as V 2 dd , and inductive coupling noise scales as V 3 dd .…”

Section: Noise Marginsmentioning

confidence: 99%

“…Burr showed that the thermal noises are as small as 100µV [16]. Practically, thermal noise is not a concern when the supply voltage is above 1V.…”

Section: Noise Marginsmentioning

confidence: 99%

“…One of the trends in today's IC market is to reduce the supply voltage [16] [17]. The effectiveness of VLV testing is based on the observation that the difference of the electrical characteristics between a faulty circuit and a faultfree circuit can be increased by reducing the supply voltage.…”

Section: Vlv Testing For Low-voltage Technologiesmentioning

confidence: 99%

See 2 more Smart Citations