CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications

Saligram, Rakshith; Datta, Suman; Raychowdhury, Arijit

doi:10.1109/cicc51472.2021.9431527

Cited by 25 publications

(15 citation statements)

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“…As discussed in the previous Section 2, bit cells in conventional eDRAMs may cause data flipping instantly after the write operation due to a sub-threshold leakage current, which can be more severe in deep submicron technology [24][25][26][27][28]. Various methods have been suggested to address those issues; however, those approaches resulted in significant area overhead or needed additional voltage boosting circuits.…”

Section: Methodsmentioning

confidence: 99%

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Kim

Park

2022

Sensors

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This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

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Section: Methodsmentioning

confidence: 99%

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Kim

Park

2022

Sensors

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“…GC-eDRAMs based on 3T topology have also been evaluated in [13], demonstrating that cache performance similar to 6T-SRAM can be obtained, while achieving higher density, comparable access speed, and lower power. A recent test-chip of 2T-based GC-eDRAM has been evaluated in the temperature range from 4 K to 300 K for various supply voltages [12]. The prototype shows outstanding improvements, in terms of data retention time, by about six orders of magnitude when cooling down from 300 K to 4 K. Therefore, GC-eDRAMs can be considered as a power-effective solution to build embedded memories operating at cryogenic temperatures.…”

Section: Deep Space Electronicsmentioning

confidence: 99%

“…The need for electronic devices capable of operating at cryogenic temperatures has always been a sought-after feature in deep space applications; however, high-performance computing and especially quantum computing are now increasing the demand for processors and memories that can operate at very low temperatures. While quantum computing systems operate in the mK range, memory sub-systems capable of operating at the liquid nitrogen boiling point (77 K) and interfacing systems operating at helium temperatures (4 K) are requested as more costeffective solutions [2,12]. This potentially enables the possibility to bridge the gap from room-temperature to cryogenic applications that operate down to 4 K and below [8].…”

Section: Introductionmentioning

confidence: 99%

“…If the SN is holding a '1', the RBL is discharged to ground, and if it is a '0', the RBL is maintained at V DD . A recent study experimentally demonstrates the GC-eDRAM capabilities when cooled down from room temperature to the helium nitrogen boiling point [12]. • STT-MRAM: This bitcell consists of a MOS access transistor and an MTJ that stores the non-volatile information.…”

Section: Introductionmentioning

confidence: 99%

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Embedded Memories for Cryogenic Applications

2021

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The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

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“…As another emerging memory device, STT-MRAM at the cryogenic operation of 77 K has been reported that it outperforms six-transistor static random access memory (6T-SRAM) in terms of both dynamic and static power, as well as read access latency [17]. CMOS compatible two-transistor gain cell (2T-Gain Cell) [18], [19] and the processing-in-memory (PIM) [20] were also investigated and resulting significant improvements at the cryogenic temperature.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

Sanuki¹,

Aiba²,

Tanaka³

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This report introduces the cryogenic operation and storage performance of 3-D flash memory. The cell transistor characteristics and the basic functionalities, including read and program and erase (P/E) operations, are investigated at an extremely low temperature of 77 K cooled by the liquid nitrogen. The cell transistor has a steep subthreshold slope at 77 K compared with at 300 K, and the read operation is fully functional even though the saturation current becomes relatively small. P/E operations at 77 K are not much different from those at 300 K, and the same incremental-step pulse programming (ISPP) and incremental-step pulse erase (ISPE) methods are applicable. In addition, the storage performance and the reliability characteristics of 3-D flash memory, such as the read noise, the disturb characteristics, the data retention, and the cycle endurance, are also investigated. While there is no degradation in the disturb characteristics, the read noise at 77 K was significantly minimized compared with that at 300 K. The data retention characteristics are about three times improved, and the cycle endurance is about ten times improved at 77 K compared with at 300 K. These storage performance improvements and high-reliability characteristics at cryogenic operation enable us to achieve the ultramultilevel cell. We show the successful demonstration of 6-bit per cell (HLC) and discuss the impact of additional cooling cost and the possibility of future storage devices beyond HLC. The cryogenic operation of 3-D flash memory can greatly improve the storage performance and opens the door for potential new applications and the bit cost scaling for future storage devices.INDEX TERMS 3-D flash memory, 6-bit per cell (HLC), 77 K, bit cost scaling, cryogenic, immersion cooling, liquid nitrogen, NAND.

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CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications

Cited by 25 publications

References 0 publications

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Embedded Memories for Cryogenic Applications

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

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