Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management

Gaspar, Lubos; Fischer, Viktor; Bossuet, Lilian; Drutarovský, Miloš

doi:10.1109/fpl.2011.99

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…This method is called MAC (MIPS-AES Crypto). The hardware implementation using FPGA provides significant performance gains compared to the software implementation using general purpose processor (microprocessor) in terms of parallel processing, pipelining, word size, and speed [22]. Throughput up to several Gbps can be easily achieved by using FPGA.…”

Section: Mips Based Aes Crypto (Mac)mentioning

confidence: 98%

FPGA implementation of AES-based crypto processor

Anwar

Daneshtalab

Ebrahimi

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.

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Section: Mips Based Aes Crypto (Mac)mentioning

confidence: 98%

FPGA implementation of AES-based crypto processor

Anwar

Daneshtalab

Ebrahimi

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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“…4. The Initial Configuration is based on a MicroBlaze -crypto-coprocessor system presented in [12]. The processor firmware is stored in an instruction memory.…”

Section: B Initial Configuration Structurementioning

confidence: 99%

Two IP protection schemes for multi-FPGA systems

Gaspar

Fischer

Güneysu

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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This paper proposes two novel protection schemes for multi-FPGA systems providing high security of IP designs licensed by IP vendors to system integrators and installed remotely in a hostile environment. In the first scheme, these useful properties are achieved by storing two different configuration keys inside an FPGA, while in the second scheme, they are obtained using a hardware white-box cipher for creating a trusted environment. Thanks to the proposed principles, FPGA configurations coming from different IP owners cannot be cloned or reverse-engineered by any involved party, including system integrator and other IP owners. The proposed schemes can be directly implemented in recent FPGAs such as Xilinx Spartan 6 and Virtex 6.

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“…However, these architectures are usually not commercially available or provide only protection against certain attack vectors. Practically realized approaches for secure key storage [9], [10] or against software exploits [11], [12] usually rely on the extension of Field Programmable Gate Array (FPGA) soft-cores or small research processing platforms. On reconfigurable hardware the designer can also exploit security features build in by the FPGA vendor [13], like bitstream encryption.…”

Section: Introductionmentioning

confidence: 99%

A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems

Ender

Duppmann

Wild

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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In this work we propose a secure architecture for Voice-over-IP (VoIP) that encapsulates all security and privacy critical components and I/O functions into secure hardware and thus drastically reduces the underlying trusted computing base. Our proof-of-concept implementation shows that high security and reliance on established standards and software (e.g., device drivers, transmission control, and protocols) to keep development costs down are no contradiction. Security is ensured as all security and privacy critical operations of the VoIP system are performed in protected hardware and as a consequence a successful attack on any software component (e.g., buffer overflow) does not lead to a violation of security. All I/O devices like microphones, speakers, displays, and dial buttons are directly connected to the secure hardware and cannot be controlled by an adversary even if the software part has been compromised.

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Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management

Cited by 6 publications

References 11 publications

FPGA implementation of AES-based crypto processor

FPGA implementation of AES-based crypto processor

Two IP protection schemes for multi-FPGA systems

A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems

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