One of the most critical issues of the STI process is the reduction of the stress generation during the oxidation steps. This stress can create defects later on in the process, leading to increased leakage. In this work microscopy analyses confirm the link between dislocations and anomalous leakage current. The leakage current of transistors and diodes is measured as a function of temperature and the dislocations responsible of this leakage are characterized by the spectrum analysis of the Emission Microscopy. However, in addition to an accurate characterization of the defects, it is necessary to identify a method to detect the formation of crystal defects at an early stage in the device fabrication process. In this paper, we describe how the passive voltage contrast in the KLA-Tencor eS31 tool is used for this purpose. 1 Introduction Shallow trench isolation (STI) is the most favourable scheme for deep submicron VLSI CMOS technology due to its high scalability and excellent isolation capability. One of the most critical issues of the STI process is the reduction of stress related defects as resulted from silicon trench etch, liner oxidation, oxide gap fill and more importantly the subsequent oxidations and high energy implantations [1]. The stress can result in defects later on in the process, especially triggered by high energy Arsenic implantation for source/drain [2]. Such defects result to many undesirable effects (e.g. diode leakage or channel leakage in transistor) resulting to low yields. It would be therefore very important to identify the steps when dislocations are generated in the process, and to characterize the electrical activity of dislocations in junctions and transistors, in order to understand how they develop and how they affect the device performance.