CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator

Paneliya, Hirenkumar; Hosseini, Morteza; Sasan, Avesta; Homayoun, Houman

doi:10.1109/isqed48828.2020.9137013

“…Convolution neural networks (CNNs) have been successfully used in computer vision tasks such as image and audio classification (Paneliya et al 2020;H.Ren et al 2020, in press;M.Hosseini et al 2020;Hosseini and Mohsenin 2020). Recently, it is also used in reinforcement learning applications (Shiri et al 2020;Prakash et al 2020;.…”

Section: Introductionmentioning

confidence: 99%

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

Khatwani

¹

,

Rashid

²

,

Paneliya

³

et al. 2022

Handbook of Biochips

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0

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Our proposed network achieves 93.14% classification accuracy using EEG dataset collected by a 64 channel BioSemi ActiveTwo headsets, averaged across 17 patients and 10 artifact classes. Our hardware architecture is fully parameterized with number of input channels, filters, depth and data bit-width. The number of processing engines (PE) in the proposed hardware can vary between 1 to 16 providing different latency, throughput, power and energy efficiency measurements. We implement our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 1.4 mJ to 4.7 mJ dynamic energy with different PE configurations. Energy consumption is further reduced by 16.7× implementing on application-specified integrated circuit at the post layout level in 65-nm CMOS technology. Our FPGA implementation is 1.7× to 5.15× higher energy efficient than some previous works. Moreover, our ASIC implementation is also 8.47× to 25.79× higher energy efficient compared to previous works. We also demonstrated that the proposed network is reconfigurable to detect artifacts from another EEG dataset collected in our lab by a 14 channel Emotiv EPOC+ headset and achieved 93.5% accuracy for eye blink artifact detection.

show abstract

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

Khatwani¹,

Rashid²,

Paneliya³

et al. 2021

Handbook of Biochips

Self Cite

0

View full text Add to dashboard Cite

Our proposed network achieves 93.14% classification accuracy using EEG dataset collected by a 64 channel BioSemi ActiveTwo headsets, averaged across 17 patients and 10 artifact classes. Our hardware architecture is fully parameterized with number of input channels, filters, depth and data bit-width. The number of processing engines (PE) in the proposed hardware can vary between 1 to 16 providing different latency, throughput, power and energy efficiency measurements. We implement our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 1.4 mJ to 4.7 mJ dynamic energy with different PE configurations. Energy consumption is further reduced by 16.7× implementing on application-specified integrated circuit at the post layout level in 65-nm CMOS technology. Our FPGA implementation is 1.7× to 5.15× higher energy efficient than some previous works. Moreover, our ASIC implementation is also 8.47× to 25.79× higher energy efficient compared to previous works. We also demonstrated that the proposed network is reconfigurable to detect artifacts from another EEG dataset collected in our lab by a 14 channel Emotiv EPOC+ headset and achieved 93.5% accuracy for eye blink artifact detection.

show abstract

A Flexible Multichannel EEG Artifact Identification Processor using Depthwise-Separable Convolutional Neural Networks

Khatwani

¹

,

Rashid

²

,

Paneliya

³

et al. 2021

J. Emerg. Technol. Comput. Syst.

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This article presents an energy-efficient and flexible multichannel Electroencephalogram (EEG) artifact identification network and its hardware using depthwise and separable convolutional neural networks. EEG signals are recordings of the brain activities. EEG recordings that are not originated from cerebral activities are termed artifacts . Our proposed model does not need expert knowledge for feature extraction or pre-processing of EEG data and has a very efficient architecture implementable on mobile devices. The proposed network can be reconfigured for any number of EEG channel and artifact classes. Experiments were done with the proposed model with the goal of maximizing the identification accuracy while minimizing the weight parameters and required number of operations. Our proposed network achieves 93.14% classification accuracy using an EEG dataset collected by 64-channel BioSemi ActiveTwo headsets, averaged across 17 patients and 10 artifact classes. Our hardware architecture is fully parameterized with number of input channels, filters, depth, and data bit-width. The number of processing engines (PE) in the proposed hardware can vary between 1 to 16, providing different latency, throughput, power, and energy efficiency measurements. We implement our custom hardware architecture on Xilinx FPGA (Artix-7), which on average consumes 1.4 to 4.7 mJ dynamic energy with different PE configurations. Energy consumption is further reduced by 16.7× implementing on application-specified integrated circuit at the post layout level in 65-nm CMOS technology. Our FPGA implementation is 1.7 × to 5.15 × higher in energy efficiency than some previous works. Moreover, our Application-Specified Integrated Circuit implementation is also 8.47 × to 25.79 × higher in energy efficiency compared to previous works. We also demonstrated that the proposed network is reconfigurable to detect artifacts from another EEG dataset collected in our lab by a 14-channel Emotiv EPOC+ headset and achieved 93.5% accuracy for eye blink artifact detection.

show abstract

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator

Cited by 3 publications

References 18 publications

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

A Flexible Software-Hardware Framework for Brain EEG Multiple Artifact Identification

A Flexible Multichannel EEG Artifact Identification Processor using Depthwise-Separable Convolutional Neural Networks

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