CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach

Abrishami, Mohammad Saeed; Pedram, Massoud; Nazarian, Shahin

doi:10.1109/iccd46524.2019.00061

Cited by 9 publications

(5 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The industry adopted multicorner multi-mode (MCMM) timing analysis and transitioned from the derating to performing sign-off at every operating condition. [1], [21], [22]. MCMM analysis requires standard cell libraries characterized at a set of PVT corners for each of the given operating voltage modes.…”

Section: B Corner Explosion and Timing Closurementioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

View full text Add to dashboard Cite

For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion: while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits-or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method's characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

show abstract

Section: B Corner Explosion and Timing Closurementioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

View full text Add to dashboard Cite

show abstract

“…This coincides with the functionality of CSM in regenerating circuit voltage waveforms. Therefore, similar to [18] and [21], we use the expected waveform similarity (E sim ) as a figure of merit for the simulation accuracy measurements. In this work, E sim is defined as the mean of the absolute difference between precise HSPICE and NN-PARS simulations relative to the supply voltage value of the technology as shown in Eq.…”

Section: A Nn Architecturementioning

confidence: 99%

“…As suggested in [18], high dimensional CSM-LUTs with large sizes can only fit in DRAM of CPUs or GPUs, while lowdimensional V-LUT tables can easily fit into L1 caches. The major shortcoming in data retrieval from DRAM is the high latency.…”

Section: Introductionmentioning

confidence: 99%

“…To mitigate this shortcoming, semi-analytical methods [20] suggest combining nonlinear analytical models and low-dimensional CSM lookup tables to simultaneously achieve high modeling accuracy in addition to low time and space complexity. On the other hand, [18] (referred to as CSM-NN method throughout the paper) proposed complete removal of the long memory queries by approximating CSM component values using simple NNs. While this method improved the simulation time of simple gates, it did not touch upon on how it can be scaled up to the level of circuit simulation, especially using parallel computation capabilities of GPUs.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework

Abrishami¹,

Ge²,

Calderon³

et al. 2020

Preprint

Self Cite

View full text Add to dashboard Cite

The shrinking of transistor geometries as well as the increasing complexity of integrated circuits, significantly aggravate nonlinear design behavior. This demands accurate and fast circuit simulation to meet the design quality and time-tomarket constraints. The existing circuit simulators which utilize lookup tables and/or closed-form expressions are either slow or inaccurate in analyzing the nonlinear behavior of designs with billions of transistors. To address these shortcomings, we present NN-PARS, a neural network (NN) based and parallelized circuit simulation framework with optimized event-driven scheduling of simulation tasks to maximize concurrency, according to the underlying GPU parallel processing capabilities. NN-PARS replaces the required memory queries in traditional techniques with parallelized NN-based computation tasks. Experimental results show that compared to a state-of-the-art current-based simulation method, NN-PARS reduces the simulation time by over two orders of magnitude in large circuits. NN-PARS also provides high accuracy levels in signal waveform calculations, with less than 2% error compared to HSPICE.

show abstract

“…Abrishami et al [1], in their work, they present CSM-NN, a scalable simulation framework with optimized neural network structures and processing algorithms [1]. Alioon and Delialioğlu [3] designed, developed, and implemented original, collaborative mobile learning activities for a computer networking course.…”

Section: Introductionmentioning

confidence: 99%

Simulation of Logic Circuit Tests on Android-Based Mobile Devices

Çakir

Çitak

2022

Jurnal Ilmiah Teknik Elektro Komputer Dan Informatika

View full text Add to dashboard Cite

In this study, an application that can run on Android and Windows-based mobile devices was developed to allow students attending such classes as Numerical/Digital Electronics, Logic Circuits, Basic Electronics Measurement, and Electronic Systems in Turkey's Vocation and Technical Education Schools to easily carry out the simulation of logic gates, as well as logic circuit tests performed using logic gates. A 2D-mobile application that runs on both platforms was developed using the C# language on the Unity3D editor. To assess the usability of the mobile application, a one-hour training session was administered in March of the 2017-2018 academic year to two groups of students from a single class in the sixth grade of an Imam Hatip Secondary School affiliated with the Ministry of National Education. Each of the two groups contained 12 students who were assumed to be equivalent and who had no prior knowledge of the subject. The training of the first group began with a lecture on basic logic gates using a blackboard and involved no simulations. In comparison, the second group was given the same lecture and received additional training involving demonstrations of the developed mobile application and its simulations. Following the lectures, a written exam was applied to both groups. An evaluation of the exam results revealed that 83 percent of the students who had been given demonstrations of the mobile application were able to perform the circuit task completely, whereas only 50 percent of the others were able to complete the task. It was concluded that the application was both useful and facilitating for the students, and it was also noted that students who were supported by the mobile application had gained a better grasp of the topic by being able to see and practice the simulations firsthand.

show abstract

CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach

Cited by 9 publications

References 29 publications

Cross-Corner Delay Variation Model for Standard Cell Libraries

Cross-Corner Delay Variation Model for Standard Cell Libraries

NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework

Simulation of Logic Circuit Tests on Android-Based Mobile Devices

Contact Info

Product

Resources

About